Lines Matching refs:GC
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
421 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
985 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
1112 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1115 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1122 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1128 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1209 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1519 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1526 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1527 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1616 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1617 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1625 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
1626 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
1627 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
1628 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
1643 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
1644 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
1645 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
1646 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
1702 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
1706 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
1708 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
1712 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
1724 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
1725 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
1737 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1753 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1759 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1774 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1785 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1793 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
1795 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
1797 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1804 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1807 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
1812 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1814 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1823 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
1837 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
1847 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1856 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1859 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1878 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
1882 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
1885 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1908 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
1911 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
2182 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
2183 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
2184 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
2186 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
2193 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2210 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2212 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2216 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2231 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2233 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2247 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2249 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2253 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2268 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2270 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2284 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2286 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2290 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2305 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2307 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2321 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2323 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2327 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2342 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2344 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2357 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
2358 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
2396 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2405 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2408 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
2454 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2456 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2460 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2475 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
2480 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
2481 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2483 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2524 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2526 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2530 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2545 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
2550 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2552 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2593 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2595 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2599 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2614 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
2619 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2621 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2666 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
2668 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2701 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
2740 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
2743 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
2751 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2761 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2764 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2766 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2779 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2782 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2796 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2800 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2801 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2805 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2806 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2810 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2812 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2816 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2819 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2820 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2822 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
2834 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2837 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2838 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2841 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2842 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2845 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2847 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2851 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2854 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2855 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2856 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2882 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2884 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2915 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2917 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2921 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2936 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
2940 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2942 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
2944 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2948 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
2951 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2954 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2970 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2973 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2975 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2995 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
3002 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
3008 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
3013 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
3035 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
3044 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
3057 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
3072 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3073 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3076 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3077 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3080 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
3083 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
3085 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
3087 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
3090 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
3091 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
3094 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
3095 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
3098 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
3101 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
3102 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
3105 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
3108 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
3242 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3249 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3279 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3289 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3317 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3333 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
3338 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3343 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3363 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3366 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3368 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3372 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
3376 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3380 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3381 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3383 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3387 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3389 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
3391 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3393 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3398 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
3400 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3404 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
3408 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
3410 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
3414 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
3418 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3420 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3424 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3426 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3431 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3433 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3437 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3441 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3443 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3447 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3449 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3453 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3457 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3649 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
3651 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
3653 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
3655 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
3656 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
3659 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
3670 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
3673 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
3675 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
3677 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3678 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3681 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
3683 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
3685 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3686 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3689 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
3691 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
3693 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3694 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3697 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
3699 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
3701 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3702 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3705 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
3707 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
3709 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3710 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3713 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
3715 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
3717 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3718 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3721 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
3723 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
3725 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3726 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3839 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3854 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
3871 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3893 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3910 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3913 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3914 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3919 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3920 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3935 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3936 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3937 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3953 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3958 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3963 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3968 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
4009 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4020 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4024 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
4035 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4046 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4055 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4061 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4064 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4068 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4071 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4076 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4082 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4085 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4088 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4092 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4095 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4108 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4113 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4115 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4122 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4125 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4129 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4132 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4138 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4148 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4157 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4160 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4167 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4170 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4174 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4176 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4181 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4281 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4286 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4295 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4300 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4305 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4328 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4329 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
4344 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4345 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
4562 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4820 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
4823 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
4867 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4870 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4873 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4876 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4990 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5009 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5080 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5082 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
5088 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5091 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5098 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5101 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5352 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
5358 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
5359 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);