dev/vme/si.c

139 	struct ncr5380_softc	ncr_sc;
227 	struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
238 	ncr_sc->sc_dev = self;
248 	ncr_sc->sc_regt = bt;
249 	ncr_sc->sc_regh = bh;
253 	ncr_sc->sc_dma_setup = si_dma_setup;
254 	ncr_sc->sc_dma_start = si_dma_start;
255 	ncr_sc->sc_dma_eop   = si_dma_stop;
256 	ncr_sc->sc_dma_stop  = si_dma_stop;
278 	ncr_sc->sci_r0 = 0;
279 	ncr_sc->sci_r1 = 1;
280 	ncr_sc->sci_r2 = 2;
281 	ncr_sc->sci_r3 = 3;
282 	ncr_sc->sci_r4 = 4;
283 	ncr_sc->sci_r5 = 5;
284 	ncr_sc->sci_r6 = 6;
285 	ncr_sc->sci_r7 = 7;
287 	ncr_sc->sc_rev = NCR_VARIANT_NCR5380;
292 	ncr_sc->sc_pio_out = ncr5380_pio_out;
293 	ncr_sc->sc_pio_in =  ncr5380_pio_in;
294 	ncr_sc->sc_dma_alloc = si_dma_alloc;
295 	ncr_sc->sc_dma_free  = si_dma_free;
296 	ncr_sc->sc_dma_poll  = si_dma_poll;
298 	ncr_sc->sc_flags = 0;
300 		ncr_sc->sc_no_disconnect = 0xFF;
302 		ncr_sc->sc_flags |= NCR5380_FORCE_POLLING;
303 	ncr_sc->sc_min_dma_len = MIN_DMA_LEN;
336 	ncr_sc->sc_channel.chan_id = 7;
337 	ncr_sc->sc_adapter.adapt_minphys = minphys;
342 	si_reset_adapter(ncr_sc);
343 	ncr5380_attach(ncr_sc);
350 		ncr_sc->sc_intr_on   = si_intr_on;
351 		ncr_sc->sc_intr_off  = si_intr_off;
362 	struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
370 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
383 		if (sc->ncr_sc.sc_state & NCR_DOINGDMA)
384 			sc->ncr_sc.sc_state |= NCR_ABORTING;
390 		claimed = ncr5380_intr(&sc->ncr_sc);
406 si_reset_adapter(struct ncr5380_softc *ncr_sc)
408 	struct si_softc *sc = (struct si_softc *)ncr_sc;
422 	SIREG_WRITE(ncr_sc, SIREG_CSR, 0);
424 	SIREG_WRITE(ncr_sc, SIREG_CSR,
428 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, 0);
429 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, 0);
430 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, 0);
431 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, 0);
432 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, 0);
433 	SIREG_WRITE(ncr_sc, SIREG_IV_AM, sc->sc_adapter_iv_am);
434 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, 0);
436 	SCI_CLR_INTR(ncr_sc);
448 si_dma_alloc(struct ncr5380_softc *ncr_sc)
450 	struct si_softc *sc = (struct si_softc *)ncr_sc;
451 	struct sci_req *sr = ncr_sc->sc_current;
468 	addr = (u_long)ncr_sc->sc_dataptr;
469 	xlen = ncr_sc->sc_datalen;
523 si_dma_free(struct ncr5380_softc *ncr_sc)
525 	struct si_softc *sc = (struct si_softc *)ncr_sc;
526 	struct sci_req *sr = ncr_sc->sc_current;
534 	if (ncr_sc->sc_state & NCR_DOINGDMA)
558 si_dma_poll(struct ncr5380_softc *ncr_sc)
560 	struct sci_req *sr = ncr_sc->sc_current;
564 	if (ncr_sc->sc_state & NCR_ABORTING)
572 		csr = SIREG_READ(ncr_sc, SIREG_CSR);
577 			    device_xname(ncr_sc->sc_dev));
606 si_intr_on(struct ncr5380_softc *ncr_sc)
611 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, 0);
612 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, 0);
613 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, 0);
614 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, 0);
617 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
620 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
628 si_intr_off(struct ncr5380_softc *ncr_sc)
632 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
634 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
650 si_dma_setup(struct ncr5380_softc *ncr_sc)
652 	struct si_softc *sc = (struct si_softc *)ncr_sc;
653 	struct sci_req *sr = ncr_sc->sc_current;
664 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
671 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
673 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
681 	xlen = ncr_sc->sc_datalen;
705 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
708 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, (uint16_t)(dva >> 16));
709 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, (uint16_t)(dva & 0xFFFF));
712 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, 0);
713 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, 0);
716 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, 0);
717 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, 0);
722 si_dma_start(struct ncr5380_softc *ncr_sc)
724 	struct si_softc *sc = (struct si_softc *)ncr_sc;
725 	struct sci_req *sr = ncr_sc->sc_current;
734 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, (uint16_t)(xlen >> 16));
735 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, (uint16_t)(xlen & 0xFFFF));
736 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, (uint16_t)(xlen >> 16));
737 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, (uint16_t)(xlen & 0xFFFF));
744 		NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT);
745 		SCI_CLR_INTR(ncr_sc);
746 		NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA);
748 		mode = NCR5380_READ(ncr_sc, sci_mode);
750 		NCR5380_WRITE(ncr_sc, sci_mode, mode);
752 		NCR5380_WRITE(ncr_sc, sci_dma_send, 0); /* start it */
754 		NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN);
755 		SCI_CLR_INTR(ncr_sc);
756 		NCR5380_WRITE(ncr_sc, sci_icmd, 0);
758 		mode = NCR5380_READ(ncr_sc, sci_mode);
760 		NCR5380_WRITE(ncr_sc, sci_mode, mode);
762 		NCR5380_WRITE(ncr_sc, sci_irecv, 0); /* start it */
765 	ncr_sc->sc_state |= NCR_DOINGDMA;
768 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
770 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
775 		    __func__, ncr_sc->sc_state);
782 si_dma_eop(struct ncr5380_softc *ncr_sc)
790 si_dma_stop(struct ncr5380_softc *ncr_sc)
792 	struct si_softc *sc = (struct si_softc *)ncr_sc;
793 	struct sci_req *sr = ncr_sc->sc_current;
799 	if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) {
806 	ncr_sc->sc_state &= ~NCR_DOINGDMA;
808 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
812 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
817 		ncr_sc->sc_state |= NCR_ABORTING;
818 		si_reset_adapter(ncr_sc);
822 	if (ncr_sc->sc_state & NCR_ABORTING)
838 	resid = SIREG_READ(ncr_sc, SIREG_FIFO_CNTH) << 16;
839 	resid |= SIREG_READ(ncr_sc, SIREG_FIFO_CNT) & 0xFFFF;
852 	if (ntrans > ncr_sc->sc_datalen)
856 	ncr_sc->sc_dataptr += ntrans;
857 	ncr_sc->sc_datalen -= ntrans;
871 		uint8_t *cp = ncr_sc->sc_dataptr;
874 		bprh = SIREG_READ(ncr_sc, SIREG_BPRH);
875 		bprl = SIREG_READ(ncr_sc, SIREG_BPRL);
904 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, 0);
905 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, 0);
907 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, 0);
908 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, 0);
910 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, 0);
911 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, 0);
913 	mode = NCR5380_READ(ncr_sc, sci_mode);
916 	NCR5380_WRITE(ncr_sc, sci_mode, mode);
917 	NCR5380_WRITE(ncr_sc, sci_icmd, 0);