Lines Matching refs:IOASIC_SLOT_1_START
68 #define IOASIC_SLOT_1_START 0x040000
89 #define IOASIC_SCSI_DMAPTR IOASIC_SLOT_1_START+0x000
90 #define IOASIC_SCSI_NEXTPTR IOASIC_SLOT_1_START+0x010
91 #define IOASIC_LANCE_DMAPTR IOASIC_SLOT_1_START+0x020
92 #define IOASIC_SCC_T1_DMAPTR IOASIC_SLOT_1_START+0x030
93 #define IOASIC_SCC_R1_DMAPTR IOASIC_SLOT_1_START+0x040
94 #define IOASIC_SCC_T2_DMAPTR IOASIC_SLOT_1_START+0x050
95 #define IOASIC_SCC_R2_DMAPTR IOASIC_SLOT_1_START+0x060
96 #define IOASIC_FLOPPY_DMAPTR IOASIC_SLOT_1_START+0x070
97 #define IOASIC_ISDN_X_DMAPTR IOASIC_SLOT_1_START+0x080
98 #define IOASIC_ISDN_X_NEXTPTR IOASIC_SLOT_1_START+0x090
99 #define IOASIC_ISDN_R_DMAPTR IOASIC_SLOT_1_START+0x0a0
100 #define IOASIC_ISDN_R_NEXTPTR IOASIC_SLOT_1_START+0x0b0
101 #define IOASIC_BUFF0 IOASIC_SLOT_1_START+0x0c0
102 #define IOASIC_BUFF1 IOASIC_SLOT_1_START+0x0d0
103 #define IOASIC_BUFF2 IOASIC_SLOT_1_START+0x0e0
104 #define IOASIC_BUFF3 IOASIC_SLOT_1_START+0x0f0
105 #define IOASIC_CSR IOASIC_SLOT_1_START+0x100
106 #define IOASIC_INTR IOASIC_SLOT_1_START+0x110
107 #define IOASIC_IMSK IOASIC_SLOT_1_START+0x120
108 #define IOASIC_CURADDR IOASIC_SLOT_1_START+0x130
109 #define IOASIC_ISDN_X_DATA IOASIC_SLOT_1_START+0x140
110 #define IOASIC_ISDN_R_DATA IOASIC_SLOT_1_START+0x150
111 #define IOASIC_LANCE_DECODE IOASIC_SLOT_1_START+0x160
112 #define IOASIC_SCSI_DECODE IOASIC_SLOT_1_START+0x170
113 #define IOASIC_SCC0_DECODE IOASIC_SLOT_1_START+0x180
114 #define IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190
115 #define IOASIC_FLOPPY_DECODE IOASIC_SLOT_1_START+0x1a0
116 #define IOASIC_SCSI_SCR IOASIC_SLOT_1_START+0x1b0
117 #define IOASIC_SCSI_SDR0 IOASIC_SLOT_1_START+0x1c0
118 #define IOASIC_SCSI_SDR1 IOASIC_SLOT_1_START+0x1d0
119 #define IOASIC_CTR IOASIC_SLOT_1_START+0x1e0 /*3max+/3000*/