Lines Matching refs:NCR5380REGS_SZ
79 #define NCR5380REGS_SZ 8
84 #define SIREG_DMA_ADDRH (NCR5380REGS_SZ + 0) /* DMA address, high word */
85 #define SIREG_DMA_ADDRL (NCR5380REGS_SZ + 2) /* DMA address, low word */
86 #define SIREG_DMA_CNTH (NCR5380REGS_SZ + 4) /* DMA count, high word */
87 #define SIREG_DMA_CNTL (NCR5380REGS_SZ + 6) /* DMA count, low word */
88 #define SIREG_UDC_DATA (NCR5380REGS_SZ + 8) /* UDC reg data */
89 #define SIREG_UDC_ADDR (NCR5380REGS_SZ + 10) /* UDC reg addr */
90 #define SIREG_FIFO_DATA (NCR5380REGS_SZ + 12) /* FIFO data */
91 #define SIREG_FIFO_CNT (NCR5380REGS_SZ + 14) /* FIFO count, low word */
92 #define SIREG_CSR (NCR5380REGS_SZ + 16) /* Control/status register */
93 #define SIREG_BPRH (NCR5380REGS_SZ + 18) /* VME byte pack, high word */
94 #define SIREG_BPRL (NCR5380REGS_SZ + 20) /* VME byte pack, low word */
95 #define SIREG_IV_AM (NCR5380REGS_SZ + 22) /* bits 0-7: intr vector;
97 #define SIREG_FIFO_CNTH (NCR5380REGS_SZ + 24) /* FIFO count, high word */
98 #define SIREG_BANK_SZ (NCR5380REGS_SZ + 26)