dev/pci/if_wm.c

796 	(void)CSR_READ((sc), WMREG_STATUS)
2303 		sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)
2349 		reg = CSR_READ(sc, WMREG_STATUS);
3090 	    (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
4708 			reg = CSR_READ(sc, WMREG_STATUS);
4725 	CSR_WRITE(sc, WMREG_STATUS, reg);
4801 		reg = CSR_READ(sc, WMREG_STATUS);
4803 			CSR_WRITE(sc, WMREG_STATUS, reg & ~STATUS_PHYRA);
5268 				reg = CSR_READ(sc, WMREG_STATUS);
5270 				CSR_WRITE(sc, WMREG_STATUS, reg);
5589 			if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA)
5870 		CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET);
10428 	status = CSR_READ(sc, WMREG_STATUS);
10726 	status = CSR_READ(sc, WMREG_STATUS);
13483 		status = CSR_READ(sc, WMREG_STATUS);
13584 			if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
13592 		status = CSR_READ(sc, WMREG_STATUS);
13658 	status = CSR_READ(sc, WMREG_STATUS);
13670 	if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD)
13704 	status = CSR_READ(sc, WMREG_STATUS);
13775 	status = CSR_READ(sc, WMREG_STATUS);
13957 		status = CSR_READ(sc, WMREG_STATUS);
17143 	uint32_t status = CSR_READ(sc, WMREG_STATUS);
17593 	uint32_t status = CSR_READ(sc, WMREG_STATUS);
18051 		status = CSR_READ(sc, WMREG_STATUS);