Lines Matching refs:CZ_PLX_WRITE
198 #define CZ_PLX_WRITE(cz, reg, val) \
244 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \
250 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \
454 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR);
457 CZ_PLX_WRITE(cz, PLX_CONTROL, reg);
462 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG);
464 CZ_PLX_WRITE(cz, PLX_CONTROL, reg);
700 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command);
926 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL);
1214 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL,
1240 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM);
1280 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM);
1441 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW);
1446 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM);