Lines Matching defs:RISC_BLOCK
99 #define RISC_BLOCK (3 << _BLK_REG_SHFT)
694 #define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */
695 #define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */
696 #define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */
697 #define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */
698 #define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */
699 #define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */
700 #define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */
701 #define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */
702 #define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */
703 #define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */
704 #define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */
705 #define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */
706 #define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */
707 #define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */
708 #define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */
709 #define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */
710 #define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */
711 #define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */
712 #define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */
713 #define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */
714 #define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */
715 #define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */
716 #define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */
717 #define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */
718 #define RISC_MTR2100 RISC_BLOCK+0x30
720 #define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */
722 #define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */
723 #define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */
724 #define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */
725 #define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */
726 #define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */
727 #define TCR RISC_BLOCK+0x46 /* W : Test Control */
728 #define TMR RISC_BLOCK+0x48 /* W : Test Mode */