sparc/dev/sw.c

162 	struct ncr5380_softc	ncr_sc;
247 	struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
254 	ncr_sc->sc_dev = self;
266 	ncr_sc->sc_regt = oba->oba_bustag;
267 	ncr_sc->sc_regh = bh;
271 	ncr_sc->sc_dma_setup = sw_dma_setup;
272 	ncr_sc->sc_dma_start = sw_dma_start;
273 	ncr_sc->sc_dma_eop   = sw_dma_stop;
274 	ncr_sc->sc_dma_stop  = sw_dma_stop;
275 	ncr_sc->sc_intr_on   = sw_intr_on;
276 	ncr_sc->sc_intr_off  = sw_intr_off;
305 	ncr_sc->sci_r0 = 0;
306 	ncr_sc->sci_r1 = 1;
307 	ncr_sc->sci_r2 = 2;
308 	ncr_sc->sci_r3 = 3;
309 	ncr_sc->sci_r4 = 4;
310 	ncr_sc->sci_r5 = 5;
311 	ncr_sc->sci_r6 = 6;
312 	ncr_sc->sci_r7 = 7;
314 	ncr_sc->sc_rev = NCR_VARIANT_NCR5380;
319 	ncr_sc->sc_pio_out = ncr5380_pio_out;
320 	ncr_sc->sc_pio_in =  ncr5380_pio_in;
321 	ncr_sc->sc_dma_alloc = sw_dma_alloc;
322 	ncr_sc->sc_dma_free  = sw_dma_free;
323 	ncr_sc->sc_dma_poll  = sw_dma_poll;
325 	ncr_sc->sc_flags = 0;
327 		ncr_sc->sc_no_disconnect = 0xFF;
329 		ncr_sc->sc_flags |= NCR5380_FORCE_POLLING;
330 	ncr_sc->sc_min_dma_len = MIN_DMA_LEN;
363 	ncr_sc->sc_channel.chan_id = 7;
364 	ncr_sc->sc_adapter.adapt_minphys = sw_minphys;
367 	sw_reset_adapter(ncr_sc);
370 	ncr5380_attach(ncr_sc);
396 	struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
404 	csr = SWREG_READ(ncr_sc, SWREG_CSR);
417 		if (sc->ncr_sc.sc_state & NCR_DOINGDMA)
418 			sc->ncr_sc.sc_state |= NCR_ABORTING;
424 		claimed = ncr5380_intr(&sc->ncr_sc);
440 sw_reset_adapter(struct ncr5380_softc *ncr_sc)
452 	SWREG_WRITE(ncr_sc, SWREG_CSR, 0);
454 	SWREG_WRITE(ncr_sc, SWREG_CSR, SW_CSR_SCSI_RES);
456 	SWREG_WRITE(ncr_sc, SWREG_DMA_ADDR, 0);
457 	SWREG_WRITE(ncr_sc, SWREG_DMA_CNT, 0);
459 	SWREG_WRITE(ncr_sc, SWREG_CSR, SW_CSR_SCSI_RES | SW_CSR_INTR_EN);
461 	SCI_CLR_INTR(ncr_sc);
475 sw_dma_alloc(struct ncr5380_softc *ncr_sc)
477 	struct sw_softc *sc = (struct sw_softc *)ncr_sc;
478 	struct sci_req *sr = ncr_sc->sc_current;
495 	addr = (u_long)ncr_sc->sc_dataptr;
496 	xlen = ncr_sc->sc_datalen;
551 sw_dma_free(struct ncr5380_softc *ncr_sc)
553 	struct sw_softc *sc = (struct sw_softc *)ncr_sc;
554 	struct sci_req *sr = ncr_sc->sc_current;
562 	if (ncr_sc->sc_state & NCR_DOINGDMA)
586 sw_dma_poll(struct ncr5380_softc *ncr_sc)
588 	struct sci_req *sr = ncr_sc->sc_current;
592 	if (ncr_sc->sc_state & NCR_ABORTING)
600 		csr = SWREG_READ(ncr_sc, SWREG_CSR);
605 			    device_xname(ncr_sc->sc_dev));
631 sw_intr_on(struct ncr5380_softc *ncr_sc)
635 	sw_dma_setup(ncr_sc);
636 	csr = SWREG_READ(ncr_sc, SWREG_CSR);
638 	SWREG_WRITE(ncr_sc, SWREG_CSR, csr);
648 sw_intr_off(struct ncr5380_softc *ncr_sc)
652 	csr = SWREG_READ(ncr_sc, SWREG_CSR);
654 	SWREG_WRITE(ncr_sc, SWREG_CSR, csr);
668 sw_dma_setup(struct ncr5380_softc *ncr_sc)
675 	csr = SWREG_READ(ncr_sc, SWREG_CSR);
677 	SWREG_WRITE(ncr_sc, SWREG_CSR, csr);
679 	SWREG_WRITE(ncr_sc, SWREG_DMA_ADDR, 0);
680 	SWREG_WRITE(ncr_sc, SWREG_DMA_CNT, 0);
685 sw_dma_start(struct ncr5380_softc *ncr_sc)
687 	struct sw_softc *sc = (struct sw_softc *)ncr_sc;
688 	struct sci_req *sr = ncr_sc->sc_current;
702 	xlen = ncr_sc->sc_datalen;
719 	csr = SWREG_READ(ncr_sc, SWREG_CSR);
725 	SWREG_WRITE(ncr_sc, SWREG_CSR, csr);
744 	SWREG_WRITE(ncr_sc, SWREG_DMA_ADDR, (u_int)(dh->dh_startingpa + adj));
745 	SWREG_WRITE(ncr_sc, SWREG_DMA_CNT, xlen - adj);
752 		NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT);
754 			adjlen = ncr5380_pio_out(ncr_sc, PHASE_DATA_OUT,
758 				    device_xname(ncr_sc->sc_dev), adjlen, adj);
760 		SCI_CLR_INTR(ncr_sc);
761 		NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA);
762 		mode = NCR5380_READ(ncr_sc, sci_mode);
764 		NCR5380_WRITE(ncr_sc, sci_mode, mode);
765 		NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 	/* start it */
767 		NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN);
769 			adjlen = ncr5380_pio_in(ncr_sc, PHASE_DATA_IN,
773 				    device_xname(ncr_sc->sc_dev), adjlen, adj);
775 		SCI_CLR_INTR(ncr_sc);
776 		NCR5380_WRITE(ncr_sc, sci_icmd, 0);
777 		mode = NCR5380_READ(ncr_sc, sci_mode);
779 		NCR5380_WRITE(ncr_sc, sci_mode, mode);
780 		NCR5380_WRITE(ncr_sc, sci_irecv, 0); 	/* start it */
785 	SWREG_WRITE(ncr_sc, SWREG_CSR, csr);
787 	ncr_sc->sc_state |= NCR_DOINGDMA;
792 		    __func__, ncr_sc->sc_state);
799 sw_dma_eop(struct ncr5380_softc *ncr_sc)
820 sw_dma_stop(struct ncr5380_softc *ncr_sc)
822 	struct sci_req *sr = ncr_sc->sc_current;
828 	if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) {
834 	ncr_sc->sc_state &= ~NCR_DOINGDMA;
837 	csr = SWREG_READ(ncr_sc, SWREG_CSR);
839 	SWREG_WRITE(ncr_sc, SWREG_CSR, csr);
861 		ncr_sc->sc_state |= NCR_ABORTING;
862 		sw_reset_adapter(ncr_sc);
866 	if (ncr_sc->sc_state & NCR_ABORTING)
877 	dva = SWREG_READ(ncr_sc, SWREG_DMA_ADDR);
886 	if (ntrans > ncr_sc->sc_datalen)
890 	ncr_sc->sc_dataptr += ntrans;
891 	ncr_sc->sc_datalen -= ntrans;
900 		char *cp = ncr_sc->sc_dataptr;
903 		bpr = SWREG_READ(ncr_sc, SWREG_BPR);
939 	SWREG_WRITE(ncr_sc, SWREG_DMA_ADDR, 0);
940 	SWREG_WRITE(ncr_sc, SWREG_DMA_CNT, 0);
943 	mode = NCR5380_READ(ncr_sc, sci_mode);
945 	NCR5380_WRITE(ncr_sc, sci_mode, mode);
946 	NCR5380_WRITE(ncr_sc, sci_icmd, 0);