Lines Matching defs:__PPCBIT
40 #define __PPCBIT(n) (1 << (31 - (n)))
43 #define __PPCBIT(n) __BIT(31-(n))
49 #define BPTR_EN __PPCBIT(0) /* Boot Page Enabled */
65 #define CS_CONFIG_EN __PPCBIT(0)
68 #define SDRAM_CFG_MEM_EN __PPCBIT(0)
69 #define SDRAM_CFG_SREN __PPCBIT(1)
70 #define SDRAM_CFG_ECC_EN __PPCBIT(2)
71 #define SDRAM_CFG_RDEN __PPCBIT(3)
75 #define SDRAM_CFG_DYN_PWR __PPCBIT(10)
88 #define ERR_MMEE __PPCBIT(0)
89 #define ERR_APEE __PPCBIT(23)
90 #define ERR_ACEE __PPCBIT(24)
91 #define ERR_MBEE __PPCBIT(28)
92 #define ERR_SBEE __PPCBIT(29)
93 #define ERR_MSEE __PPCBIT(31)
100 #define CATTR_VLD __PPCBIT(31)
140 #define PEX_CONFIG_ADDR_EN __PPCBIT(0)
160 #define PEXOWAR_EN __PPCBIT(0) /* enable window */
161 #define PEXOWAR_ROE __PPCBIT(3) /* relaxed ordering enable */
162 #define PEXOWAR_NS __PPCBIT(4) /* no snoop enable */
183 #define PEXIWAR_EN __PPCBIT(0) /* enable window */
184 #define PEXIWAR_PF __PPCBIT(3) /* prefetchable */
252 #define PEXERRDR_ICCA __PPCBIT(14)
279 #define L2CTL_L2E __PPCBIT(0)
280 #define L2CTL_L2I __PPCBIT(1)
283 #define L2CTL_L2DO __PPCBIT(9)
284 #define L2CTL_L2IO __PPCBIT(10)
285 #define L2CTL_L2INTDIS __PPCBIT(12)
287 #define L2CTL_L2LO __PPCBIT(18)
288 #define L2CTL_L2SLC __PPCBIT(19)
289 #define L2CTL_L2LFR __PPCBIT(21)
291 #define L2CTL_L2STASHDIS __PPCBIT(28)
318 #define SPMODE_EN __PPCBIT(0) /* Enable eSPI: 0=disabled, 1=enabled */
319 #define SPMODE_LOOP __PPCBIT(1) /* Loop mode: 0=normal, 1=loopback */
320 #define SPMODE_OD __PPCBIT(2) /* P1023: Open drain mode: 0=actively driven, 1=open drain */
327 #define SPIE_TXE __PPCBIT(16) /* Tx FIFO is empty */
328 #define SPIE_DON __PPCBIT(17) /* Last character was transmitted */
329 #define SPIE_RXT __PPCBIT(18) /* Rx FIFO has more than RXTHR bytes */
330 #define SPIE_RXF __PPCBIT(19) /* Rx FIFO is full */
331 #define SPIE_TXT __PPCBIT(20) /* Tx FIFO has less than TXTHR bytes */
332 #define SPIE_RNE __PPCBIT(22) /* Not empty: 0=empty, 1=not empty */
333 #define SPIE_TNF __PPCBIT(23) /* Tx FIFO not full: 0=full, 1=not full */
335 #define SPIM_TXE __PPCBIT(16)
336 #define SPIM_DON __PPCBIT(17)
337 #define SPIM_RXT __PPCBIT(18)
338 #define SPIM_RXF __PPCBIT(19)
339 #define SPIM_TXT __PPCBIT(20)
340 #define SPIM_RNE __PPCBIT(22)
341 #define SPIM_TNF __PPCBIT(23)
344 #define SPCOM_RXDELAY __PPCBIT(2) /* 0=normal eSPI operation */
345 #define SPCOM_DO __PPCBIT(3) /* 0=normal eSPI operation, 1=Winbond dual output read */
346 #define SPCOM_TO __PPCBIT(4) /* Transmit only: 0=normal operation, 1=No reception is done for the frame */
347 #define SPCOM_HLD __PPCBIT(5) /* 0=normal operation, 1=Mask first generated SPI_CLK */
348 #define SPCOM_LS __PPCBIT(6) /* P1023: Late sample: 0=normal operation, 1=Late data sample */
358 #define SPMODEn_CI __PPCBIT(0) /* Clock invert: 0=inactive state of SPI_CLK is low, 1=high */
359 #define SPMODEn_CP __PPCBIT(1) /* Clock phase: SPI_CLK starts toggling at the middle of the data transfer, 1=beginning */
360 #define SPMODEn_REV __PPCBIT(2) /* Reverse data mode: 0=LSB of the character sent and received first, 1=MSB */
361 #define SPMODEn_DIV16 __PPCBIT(3) /* Divide by 16: 0=System clock, 1=System clock/16 */
363 #define SPMODEn_ODD __PPCBIT(8) /* 0=Even division, 1=Odd dividion */
364 #define SPMODEn_POL __PPCBIT(11) /* CS polarity: 0=Asserted high/Negated low, 1=Asserted low/Negated high */
381 #define USB_EN __PPCBIT(29)
382 #define USB_ULPI_INT_EN __PPCBIT(31)
406 #define DCR_SNOOP __PPCBIT(25) /* DMA transactions are snooped */
407 #define DCR_RD_SAFE __PPCBIT(29) /* memory is read safe */
408 #define DCR_RD_PFE __PPCBIT(30) /* memory is prefetch safe */
409 #define DCR_RD_PF_SIZE __PPCBIT(31) /* prefetch size is 32-bytes */
424 #define PCI1_CLK_SEL __PPCBIT(16)
425 #define PCI2_CLK_SEL __PPCBIT(17)
442 #define PORDEVSR_ECW1 __PPCBIT(0)
443 #define PORDEVSR_ECW2 __PPCBIT(1)
444 #define PORDEVSR_SGMII1_DIS1 __PPCBIT(2)
445 #define PORDEVSR_SGMII1_DIS2 __PPCBIT(3)
446 #define PORDEVSR_SGMII1_DIS3 __PPCBIT(4)
447 #define PORDEVSR_SGMII1_DIS4 __PPCBIT(5)
449 #define PORDEVSR_PCI1 __PPCBIT(8)
496 #define PORDEVSR_PCI2_ARB __PPCBIT(13)
497 #define PORDEVSR_PCI1_ARB __PPCBIT(14)
498 #define PORDEVSR_PCI32 __PPCBIT(15)
501 #define PORDEVSR_PCI1_SPD __PPCBIT(16)
502 #define PORDEVSR_PCI2_SPD __PPCBIT(17)
503 #define PORDEVSR_SYS_SPD __PPCBIT(17) /* MPC8536 */
504 #define PORDEVSR_CORE_SPD __PPCBIT(18) /* MPC8536 */
508 #define PORDEVSR_FEC_DIS __PPCBIT(24)
509 #define PORDEVSR_RTPE __PPCBIT(25)
510 #define PORDEVSR_RIO_CTLS __PPCBIT(28)
518 #define GPIOCR_TX2 __PPCBIT(6) /* Enable TSEC2_TX[7:0] as GP output */
519 #define GPIOCR_RX2 __PPCBIT(7) /* Enable TSEC2_RX[7:0] as GP input */
520 #define GPIOCR_PCIOUT __PPCBIT(14) /* Enable PCI2_AD[15:8] as GP output */
521 #define GPIOCR_PCIIN __PPCBIT(15) /* Enable PCI2_AD[7:0] as GP input */
522 #define GPIOCR_GPOUT __PPCBIT(22) /* Enable GPOUT[24:31] as GP output */
532 #define PMUXCR_SD_DATA __PPCBIT(0)
533 #define PMUXCR_SDHC_CD __PPCBIT(1)
534 #define PMUXCR_SDHC_WP __PPCBIT(2)
535 #define PMUXCR_PCI_REQGNT3 __PPCBIT(3)
536 #define PMUXCR_TSEC1_TS __PPCBIT(3)
537 #define PMUXCR_PCI_REQGNT4 __PPCBIT(4)
538 #define PMUXCR_TSEC2_TS __PPCBIT(4)
539 #define PMUXCR_USB1 __PPCBIT(5)
540 #define PMUXCR_TSEC3_TS __PPCBIT(5)
541 #define PMUXCR_USB2 __PPCBIT(6)
543 #define PMUXCR_USB __PPCBIT(6)
544 #define PMUXCR_TSEC1 __PPCBIT(14)
545 #define PMUXCR_DMA0 __PPCBIT(14)
546 #define PMUXCR_DMA2 __PPCBIT(15)
547 #define PMUXCR_QE0 __PPCBIT(16)
548 #define PMUXCR_QE1 __PPCBIT(17)
549 #define PMUXCR_QE2 __PPCBIT(18)
550 #define PMUXCR_QE3 __PPCBIT(19)
551 #define PMUXCR_QE8 __PPCBIT(24)
552 #define PMUXCR_QE9 __PPCBIT(25)
553 #define PMUXCR_QE10 __PPCBIT(26)
554 #define PMUXCR_QE11 __PPCBIT(27)
555 #define PMUXCR_QE12 __PPCBIT(28)
556 #define PMUXCR_DMA1 __PPCBIT(30)
557 #define PMUXCR_DMA3 __PPCBIT(31)
563 #define DEVDISR_PCI1 __PPCBIT(0)
564 #define DEVDISR_QMAN_BMAN __PPCBIT(0) /* P1023 */
565 #define DEVDISR_PCI2 __PPCBIT(1)
566 #define DEVDISR_FMAN __PPCBIT(1) /* P1023 */
567 #define DEVDISR_PCIE __PPCBIT(2)
568 #define DEVDISR_MACSEC __PPCBIT(3) /* P1023 */
569 #define DEVDISR_LBC __PPCBIT(4)
570 #define DEVDISR_PCIE2 __PPCBIT(5)
571 #define DEVDISR_PCIE3 __PPCBIT(6)
572 #define DEVDISR_SEC __PPCBIT(7)
573 #define DEVDISR_PME __PPCBIT(8)
574 #define DEVDISR_USB1 __PPCBIT(8) /* MPC8536 */
575 #define DEVDISR_TLU1 __PPCBIT(9)
576 #define DEVDISR_USB2 __PPCBIT(9) /* MPC8536 */
577 #define DEVDISR_TLU2 __PPCBIT(10)
578 #define DEVDISR_ESDHC_10 __PPCBIT(10)
579 #define DEVDISR_USB3 __PPCBIT(10) /* MPC8536 */
580 #define DEVDISR_L2 __PPCBIT(11) /* MPC8536 */
581 #define DEVDISR_SRIO __PPCBIT(12)
582 #define DEVDISR_ESDHC_12 __PPCBIT(12) /* MPC8536 */
583 #define DEVDISR_RMSG __PPCBIT(13)
584 #define DEVDISR_SATA1 __PPCBIT(13) /* MPC8536 */
585 #define DEVDISR_DDR2_14 __PPCBIT(14)
586 #define DEVDISR_DDR_15 __PPCBIT(15)
587 #define DEVDISR_SPI_15 __PPCBIT(15) /* MPC8536 */
588 #define DEVDISR_E500 __PPCBIT(16)
589 #define DEVDISR_DDR_16 __PPCBIT(16) /* MPC8536 */
590 #define DEVDISR_TB __PPCBIT(17)
591 #define DEVDISR_E500_1 __PPCBIT(18)
592 #define DEVDISR_TB_1 __PPCBIT(19)
593 #define DEVDISR_SATA2 __PPCBIT(20) /* MPC8536 */
594 #define DEVDISR_DMA __PPCBIT(21)
595 #define DEVDISR_DMA2 __PPCBIT(22)
596 #define DEVDISR_SRDS2 __PPCBIT(22) /* MPC8536 */
597 #define DEVDISR_TSEC1 __PPCBIT(24)
598 #define DEVDISR_TSEC2 __PPCBIT(25)
599 #define DEVDISR_TSEC3 __PPCBIT(26)
600 #define DEVDISR_TSEC4 __PPCBIT(27)
601 #define DEVDISR_FEC __PPCBIT(28)
602 #define DEVDISR_SPI_28 __PPCBIT(28) /* P2020 */
603 #define DEVDISR_I2C __PPCBIT(29)
604 #define DEVDISR_DUART __PPCBIT(30)
605 #define DEVDISR_SRDS1 __PPCBIT(31) /* MPC8536 */
639 #define HRESET_REQ __PPCBIT(30) /* hardware reset request */
668 #define BR_WP __PPCBIT(23)
680 #define BR_V __PPCBIT(31)
684 #define OR_BCTLD __PPCBIT(19)
685 #define OR_CSNT __PPCBIT(20)
687 #define OR_XACS __PPCBIT(23)
689 #define OR_SETA __PPCBIT(28)
690 #define OR_TRLX __PPCBIT(29)
691 #define OR_EHTR __PPCBIT(30)
692 #define OR_EAD __PPCBIT(31)
727 #define LTESR_BM __PPCBIT(0)
728 #define LTESR_FCT __PPCBIT(1)
729 #define LTESR_PAR __PPCBIT(2)
730 #define LTESR_WP __PPCBIT(5)
731 #define LTESR_ATMW __PPCBIT(8)
732 #define LTESR_ATMR __PPCBIT(9)
733 #define LTESR_CS __PPCBIT(12)
734 #define LTESR_UCC __PPCBIT(30)
735 #define LTESR_CC __PPCBIT(31)
737 #define LTEDR_BMD __PPCBIT(0)
738 #define LTEDR_FCTD __PPCBIT(1)
739 #define LTEDR_PARD __PPCBIT(2)
740 #define LTEDR_WPD __PPCBIT(5)
741 #define LTEDR_WARA __PPCBIT(8)
742 #define LTEDR_RAWA __PPCBIT(9)
743 #define LTEDR_CSD __PPCBIT(12)
744 #define LTEDR_UCCD __PPCBIT(30)
745 #define LTEDR_CCD __PPCBIT(31)
747 #define LTEIR_BMI __PPCBIT(0)
748 #define LTEIR_FCTI __PPCBIT(1)
749 #define LTEIR_PARI __PPCBIT(2)
750 #define LTEIR_WPI __PPCBIT(5)
751 #define LTEIR_WARA __PPCBIT(8)
752 #define LTEIR_RAWA __PPCBIT(9)
753 #define LTEIR_CSI __PPCBIT(12)
754 #define LTEIR_UCCI __PPCBIT(30)
755 #define LTEIR_CCI __PPCBIT(31)
757 #define LTEATR_RWB __PPCBIT(3)
761 #define LTEATR_V __PPCBIT(31)
771 #define FMR_BOOT __PPCBIT(20)
772 #define FMR_ECCM __PPCBIT(23)
809 #define FPAR_S_MS __PPCBIT(22) /* Main(0)/Spare(1) */
812 #define FPAR_L_MS __PPCBIT(20) /* Main(0)/Spare(1) */
817 #define FECC_V __PPCBIT(0)
818 #define FECC_ECC __PPCBIT(8,31)
823 #define MXMR_RFEN __PPCBIT(1) /* Refresh enable */
829 #define MXMR_UWPL __PPCBIT(3) /* LUPWAIT is active low */
845 #define MXMR_GPL4 __PPCBIT(13) /* LGPL4 output line disable */