Lines Matching refs:VR4181_GIU81_ADDR
242 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PIOD_L_REG_W, 0xffff);
243 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE0_REG_W,
256 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE1_REG_W, GP8_GPO);
268 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE2_REG_W,
281 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE3_REG_W,
298 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PIOD_L_REG_W, 0xffff);
299 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE0_REG_W,
314 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE1_REG_W,
328 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE2_REG_W,
341 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE3_REG_W,
356 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_INTTYP_L_REG_W,
358 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_INTMASK_REG_W,
360 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_INTEN_REG_W, GIEN4);
374 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PCS0STRA_REG_W, 0x0000);
375 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PCS0STPA_REG_W, 0x0fff);
376 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PCS0HIA_REG_W, 0x1401);
377 REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PCSMODE_REG_W,