Lines Matching refs:csr
97 uint32_t csr;
229 pcireg_t csr;
245 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
246 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
247 csr &= ~PCI_COMMAND_MASTER_ENABLE;
248 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
290 if ((q != self) && (q->csr & what)) {
333 pcireg_t csr, address, mask;
338 csr = 0;
355 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
368 if (csr & (PCI_COMMAND_MEM_ENABLE |
373 p->csr = csr;
397 p->csr = csr;
421 if ((csr & PCI_COMMAND_IO_ENABLE) != 0)
443 if ((csr & PCI_COMMAND_MEM_ENABLE) != 0)
460 csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT);
461 csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT);
462 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr);
481 csr = pci_conf_read(pc, tag, PIIX_PCIB_MBIRQ0);
482 csr &= ~0x0000ffff;
484 csr |= 0x0000800f;
485 pci_conf_write(pc, tag, PIIX_PCIB_MBIRQ0, csr);
505 if ((p->csr & PCI_COMMAND_MEM_ENABLE) == 0) {
554 csr = pci_conf_read(pc, p->tag,
556 csr |= PCI_COMMAND_MEM_ENABLE |
559 PCI_COMMAND_STATUS_REG, csr);
560 p->csr = csr;
574 if (!(p->csr & PCI_COMMAND_IO_ENABLE)) {
599 csr = pci_conf_read(pc, p->tag,
601 csr |= PCI_COMMAND_IO_ENABLE |
604 PCI_COMMAND_STATUS_REG, csr);
605 p->csr = csr;