arm/ti/if_cpsw.c

208 cpsw_write_4(struct cpsw_softc * const sc, bus_size_t const offset,
581 	cpsw_write_4(sc, MDIOCONTROL,
584 	cpsw_write_4(sc, CPSW_ALE_CONTROL, ALECTL_CLEAR_TABLE);
730 			cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0),
792 	cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) |
818 	cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | (1 << 30) |
909 	cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
914 	cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
919 	cpsw_write_4(sc, CPSW_ALE_CONTROL,
927 		cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
931 		cpsw_write_4(sc, CPSW_SL_RX_PRI_MAP(i), 0x76543210);
932 		cpsw_write_4(sc, CPSW_PORT_P_TX_PRI_MAP(i+1), 0x33221100);
933 		cpsw_write_4(sc, CPSW_SL_RX_MAXLEN(i), 0x5f2);
935 		cpsw_write_4(sc, CPSW_PORT_P_SA_HI(i+1),
938 		cpsw_write_4(sc, CPSW_PORT_P_SA_LO(i+1),
946 		cpsw_write_4(sc, CPSW_SL_MACCONTROL(i), macctl);
949 		cpsw_write_4(sc, CPSW_ALE_PORTCTL(i+1), 3);
953 	cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210);
954 	cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0);
957 	cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 3);
962 	cpsw_write_4(sc, CPSW_SS_PTYPE, 0);
963 	cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7);
965 	cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
970 		cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
971 		cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0);
972 		cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0);
973 		cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0);
982 	cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0);
994 	cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
997 	cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, ETHER_ALIGN);
1000 	cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF);
1001 	cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF);
1004 	cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1);
1005 	cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1);
1008 	cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 1);
1009 	cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 1);
1010 	cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F);
1013 	cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 2);
1016 	cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1);
1017 	cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 1);
1020 	cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH);
1021 	cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX);
1022 	cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX);
1023 	cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC);
1027 	cpsw_write_4(sc, MDIOCONTROL,
1033 	cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(0), cpsw_rxdesc_paddr(sc, 0));
1062 	cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 1);
1063 	cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 1);
1064 	cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0x0);
1065 	cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0x0);
1066 	cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x0);
1068 	cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0);
1069 	cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0);
1082 	cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
1087 	cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
1092 		cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
1098 	cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
1143 	cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH);
1222 		cpsw_write_4(sc, CPSW_CPDMA_RX_CP(0),
1233 	cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX);
1262 		cpsw_write_4(sc, CPSW_CPDMA_TX_CP(0), 0xfffffffc);
1263 		cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 0);
1317 			cpsw_write_4(sc, CPSW_CPDMA_TX_CP(0),
1329 	cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX);
1334 			cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0),
1388 		cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, dmastat);
1393 	cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC);
1466 	cpsw_write_4(sc, CPSW_PORT_P_SA_HI(port),
1468 	cpsw_write_4(sc, CPSW_PORT_P_SA_LO(port),
1475 	cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023);
1485 	cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]);
1486 	cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]);
1487 	cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]);
1488 	cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023));