arm/ti/if_cpsw.c

202 cpsw_read_4(struct cpsw_softc * const sc, bus_size_t const offset)
722 		    cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)),
723 		    cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)), txstart, eopi);
776 		if ((cpsw_read_4(sc, reg) & __BIT(31)) == 0)
798 	v = cpsw_read_4(sc, MDIOUSERACCESS0);
824 	v = cpsw_read_4(sc, MDIOUSERACCESS0);
910 	while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
915 	while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
928 		while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
966 	while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
1083 	while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
1088 	while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
1093 		while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
1099 	while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
1169 		    cpsw_read_4(sc, CPSW_CPDMA_RX_CP(0)), 0, 0);
1258 	tx0_cp = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0));
1269 		tx0_cp = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0));
1332 		if (cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)) == 0) {
1342 	    cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)),
1343 	    cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)), 0, 0);
1362 	miscstat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0));
1370 		dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED);
1375 		stat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS);
1377 		stat = cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0));
1379 		stat = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0));
1381 		stat = cpsw_read_4(sc, CPSW_CPDMA_RX_HDP(0));
1383 		stat = cpsw_read_4(sc, CPSW_CPDMA_RX_CP(0));
1389 		dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED);
1476 	ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0);
1477 	ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1);
1478 	ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2);