Lines Matching defs:DMA_WRITE
128 #define DMA_WRITE(sc, reg, val) \
161 DMA_WRITE(sc, DMA_IRQ_EN_REG, irqen);
183 DMA_WRITE(sc, DMA_IRQ_EN_REG, irqen);
223 DMA_WRITE(sc, NDMA_SRC_ADDR_REG(ch->ch_index), src);
224 DMA_WRITE(sc, NDMA_DEST_ADDR_REG(ch->ch_index), dst);
225 DMA_WRITE(sc, NDMA_BC_REG(ch->ch_index), req->dreq_segs[0].ds_len);
226 DMA_WRITE(sc, NDMA_CTRL_REG(ch->ch_index), cfg | NDMA_CTRL_LOAD);
264 DMA_WRITE(sc, DDMA_SRC_ADDR_REG(ch->ch_index), src);
265 DMA_WRITE(sc, DDMA_DEST_ADDR_REG(ch->ch_index), dst);
266 DMA_WRITE(sc, DDMA_BC_REG(ch->ch_index), req->dreq_segs[0].ds_len);
267 DMA_WRITE(sc, DDMA_PARA_REG(ch->ch_index), DDMA_PARA_VALUE);
268 DMA_WRITE(sc, DDMA_CTRL_REG(ch->ch_index), cfg | DDMA_CTRL_LOAD);
298 DMA_WRITE(sc, NDMA_CTRL_REG(ch->ch_index), val);
302 DMA_WRITE(sc, DDMA_CTRL_REG(ch->ch_index), val);
324 DMA_WRITE(sc, DMA_IRQ_PEND_STAS_REG, pend);
392 DMA_WRITE(sc, DMA_IRQ_EN_REG, 0);
393 DMA_WRITE(sc, DMA_IRQ_PEND_STAS_REG, ~0);
405 DMA_WRITE(sc, NDMA_CTRL_REG(index), 0);
407 DMA_WRITE(sc, DDMA_CTRL_REG(index), 0);