arm/rockchip/rk_eqos.c

109 rk3588_eqos_set_mode_rgmii(struct rk_eqos_softc *rk_sc,
112 	const int id = rk_sc->sc_id;
128 	syscon_lock(rk_sc->sc_grf);
129 	syscon_write_4(rk_sc->sc_grf, RK3588_GRF_GMAC_TXRXCLK_DELAY_EN_REG,
134 	syscon_write_4(rk_sc->sc_grf, RK3588_GRF_GMAC_TXRX_DELAY_CFG_REG(id),
139 	syscon_unlock(rk_sc->sc_grf);
141 	syscon_lock(rk_sc->sc_php_grf);
142 	syscon_write_4(rk_sc->sc_php_grf, RK3588_GRF_GMAC_PHY_REG,
146 	syscon_write_4(rk_sc->sc_php_grf, RK3588_GRF_GMAC_CLK_REG,
150 	syscon_unlock(rk_sc->sc_php_grf);
154 rk3588_eqos_set_speed_rgmii(struct rk_eqos_softc *rk_sc, int speed)
156 	const int id = rk_sc->sc_id;
172 	syscon_lock(rk_sc->sc_php_grf);
173 	syscon_write_4(rk_sc->sc_php_grf, RK3588_GRF_GMAC_CLK_REG,
176 	syscon_unlock(rk_sc->sc_php_grf);
180 rk3588_eqos_clock_selection(struct rk_eqos_softc *rk_sc, int phandle)
182 	const int id = rk_sc->sc_id;
199 		syscon_lock(rk_sc->sc_php_grf);
200 		syscon_write_4(rk_sc->sc_php_grf, RK3588_GRF_GMAC_CLK_REG,
207 		syscon_unlock(rk_sc->sc_php_grf);
212 rk3588_eqos_get_unit(struct rk_eqos_softc *rk_sc, int phandle)
293 	struct rk_eqos_softc * const rk_sc = device_private(self);
294 	struct eqos_softc * const sc = &rk_sc->sc_base;
309 		rk_sc->sc_id = ops->get_unit(rk_sc, phandle);
316 	rk_sc->sc_grf = fdtbus_syscon_acquire(phandle, "rockchip,grf");
317 	if (rk_sc->sc_grf == NULL) {
321 	rk_sc->sc_php_grf = fdtbus_syscon_acquire(phandle, "rockchip,php_grf");
322 	if (rk_sc->sc_php_grf == NULL) {
361 		ops->clock_selection(rk_sc, phandle);
373 		ops->set_mode_rgmii(rk_sc, tx_delay, rx_delay);
379 			ops->set_speed_rgmii(rk_sc, IFM_1000_T);