arm/marvell/mvsoc.c

211 #if defined(MV78XX0)
349 #if defined(MV78XX0)
350 #undef MV78XX0
351 #define MV78XX0(m)	MARVELL_MV78XX0_ ## m
410 #if defined(MV78XX0)
411 	{ MV78XX0(MV78100),	1, "MV78100",	"A0",  "Discovery Innovation" },
412 	{ MV78XX0(MV78100),	2, "MV78100",	"A1",  "Discovery Innovation" },
413 	{ MV78XX0(MV78200),	1, "MV78200",	"A0",  "Discovery Innovation" },
512 #if defined(MV78XX0)
513 	{ MV78XX0(MV78100),	1, ddr_tags },
514 	{ MV78XX0(MV78100),	2, ddr_tags },
515 	{ MV78XX0(MV78200),	1, ddr_tags },
729 #if defined(MV78XX0)
730     { MV78XX0(MV78100),	"mvsoctmr",0, MVSOC_TMR_BASE,	MV78XX0_IRQ_TIMER0 },
731     { MV78XX0(MV78100),	"mvsocgpp",0, MVSOC_GPP_BASE,	MV78XX0_IRQ_GPIO0_7 },
732     { MV78XX0(MV78100),	"com",	   0, MVSOC_COM0_BASE,	MV78XX0_IRQ_UART0 },
733     { MV78XX0(MV78100),	"com",	   1, MVSOC_COM1_BASE,	MV78XX0_IRQ_UART1 },
734     { MV78XX0(MV78100),	"com",	   2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 },
735     { MV78XX0(MV78100),	"com",	   3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 },
736     { MV78XX0(MV78100),	"gttwsi",  0, MVSOC_TWSI_BASE,	MV78XX0_IRQ_TWSI0 },
737     { MV78XX0(MV78100),	"gttwsi",  1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 },
738     { MV78XX0(MV78100), "mvgbec",  0, MV78XX0_GBE0_BASE,IRQ_DEFAULT },
739     { MV78XX0(MV78100), "mvgbec",  1, MV78XX0_GBE1_BASE,IRQ_DEFAULT },
740     { MV78XX0(MV78100), "mvsata",  0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA },
742     { MV78XX0(MV78200),	"mvsoctmr",0, MVSOC_TMR_BASE,	MV78XX0_IRQ_TIMER0 },
743     { MV78XX0(MV78200),	"mvsocgpp",0, MVSOC_GPP_BASE,	MV78XX0_IRQ_GPIO0_7 },
744     { MV78XX0(MV78200),	"com",     0, MVSOC_COM0_BASE,	MV78XX0_IRQ_UART0 },
745     { MV78XX0(MV78200),	"com",     1, MVSOC_COM1_BASE,	MV78XX0_IRQ_UART1 },
746     { MV78XX0(MV78200),	"com",	   2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 },
747     { MV78XX0(MV78200),	"com",	   3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 },
748     { MV78XX0(MV78200),	"gttwsi",  0, MVSOC_TWSI_BASE,	MV78XX0_IRQ_TWSI0 },
749     { MV78XX0(MV78200),	"gttwsi",  1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 },
750     { MV78XX0(MV78200), "mvgbec",  0, MV78XX0_GBE0_BASE,IRQ_DEFAULT },
751     { MV78XX0(MV78200), "mvgbec",  1, MV78XX0_GBE1_BASE,IRQ_DEFAULT },
752     { MV78XX0(MV78200), "mvgbec",  2, MV78XX0_GBE2_BASE,IRQ_DEFAULT },
753     { MV78XX0(MV78200), "mvgbec",  3, MV78XX0_GBE3_BASE,IRQ_DEFAULT },
754     { MV78XX0(MV78200), "mvsata",  0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA },