arm/imx/imx31_icu.c

76 #define	INTC_READ(avic, reg) \
77 	bus_space_read_4((avic)->avic_memt, (avic)->avic_memh, (reg))
78 #define	INTC_WRITE(avic, reg, val) \
79 	bus_space_write_4((avic)->avic_memt, (avic)->avic_memh, (reg), (val))
86 	struct avic_softc * const avic = (void *) pic;
89 		INTC_WRITE(avic, IMX31_INTENABLEL, irq_mask);
91 		INTC_WRITE(avic, IMX31_INTENABLEH, irq_mask);
98 		INTC_WRITE(avic, IMX31_INTENNUM, irq_base);
106 	struct avic_softc * const avic = (void *) pic;
109 		INTC_WRITE(avic, IMX31_INTDISABLEL, irq_mask);
111 		INTC_WRITE(avic, IMX31_INTDISABLEH, irq_mask);
118 		INTC_WRITE(avic, IMX31_INTDISNUM, irq_base);
126 	struct avic_softc * const avic = (void *) pic;
136 	v = INTC_READ(avic, priority_reg);
139 	INTC_WRITE(avic, priority_reg, v);
155 	struct avic_softc * const avic = device_lookup_private(&avic_cd, 0);
156 	struct pic_softc * const pic = &avic->avic_pic;
161 	saved_nimask = INTC_READ(avic, IMX31_NIMASK);
163 		irq = INTC_READ(avic, IMX31_NIVECSR);
187 		INTC_WRITE(avic, IMX31_NIMASK, ipl);
199 		INTC_WRITE(avic, IMX31_NIMASK, saved_nimask);
206 CFATTACH_DECL_NEW(avic, sizeof(struct avic_softc),
223 	struct avic_softc * const avic = device_private(self);
233 	avic->avic_memt = ahba->ahba_memt;
234 	error = bus_space_map(avic->avic_memt, ahba->ahba_addr, ahba->ahba_size,
235 	    0, &avic->avic_memh);
241 	avic->avic_pic.pic_ops = &avic_pic_ops;
242 	avic->avic_pic.pic_maxsources = 64;
243 	strlcpy(avic->avic_pic.pic_name, device_xname(self),
244 	    sizeof(avic->avic_pic.pic_name));
246 	pic_add(&avic->avic_pic, ahba->ahba_irqbase);