arm/at91/at91emac.c

83 #define EMAC_WRITE(x, y) \
87 #define EMAC_WRITE(x, y) ETHREG(x) = (y)
145 	EMAC_WRITE(ETH_CTL, 0);			// disable everything
146 	EMAC_WRITE(ETH_IDR, -1);		// disable interrupts
147 	EMAC_WRITE(ETH_RBQP, 0);		// clear receive
148 	EMAC_WRITE(ETH_CFG,
150 	EMAC_WRITE(ETH_TCR, 0);			// send nothing
153 	EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
157 	EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
208 		/*EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/
239 		EMAC_WRITE(ETH_RSR, ETH_RSR_BNA);	// clear interrupt
241 		EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);	// disable receiver
242 		EMAC_WRITE(ETH_RSR, ETH_RSR_BNA);	// clear BNA bit
243 		EMAC_WRITE(ETH_CTL, ctl |  ETH_CTL_RE);	// re-enable receiver
249 		EMAC_WRITE(ETH_RSR, ETH_RSR_OVR);	// clear interrupt
338 	EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);	// disable everything
339 	EMAC_WRITE(ETH_IDR, -1);		// disable interrupts
340 	EMAC_WRITE(ETH_RBQP, 0);		// clear receive
341 	EMAC_WRITE(ETH_CFG,
343 	EMAC_WRITE(ETH_TCR, 0);			// send nothing
346 	EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
350 	EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
353 	EMAC_WRITE(ETH_CFG,
355 	EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);
361 	EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24)
364 	EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8)
366 	EMAC_WRITE(ETH_SA2L, 0);
367 	EMAC_WRITE(ETH_SA2H, 0);
368 	EMAC_WRITE(ETH_SA3L, 0);
369 	EMAC_WRITE(ETH_SA3H, 0);
370 	EMAC_WRITE(ETH_SA4L, 0);
371 	EMAC_WRITE(ETH_SA4H, 0);
456 	EMAC_WRITE(ETH_RBQP, (uint32_t)addr);
474 	EMAC_WRITE(ETH_IDR, -1);
475 	EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE
480 	EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
510 	EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD
528 	EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR
554 	EMAC_WRITE(ETH_CFG, reg);
613 		EMAC_WRITE(ETH_IER, ETH_ISR_TBRE);
682 	EMAC_WRITE(ETH_TAR, segs->ds_addr);
683 	EMAC_WRITE(ETH_TCR, m->m_pkthdr.len);
712 	EMAC_WRITE(ETH_IDR, -1);
713 	EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE
717 	EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
734 	EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);	// disable everything
735 	EMAC_WRITE(ETH_IDR, -1);		// disable interrupts
736 //	EMAC_WRITE(ETH_RBQP, 0);		// clear receive
737 	EMAC_WRITE(ETH_CFG,
739 	EMAC_WRITE(ETH_TCR, 0);			// send nothing
742 	EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
746 	EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
771 	EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
830 	EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24)
833 	EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8)
840 		EMAC_WRITE(ETH_SA2L, (ias[0][3] << 24)
843 		EMAC_WRITE(ETH_SA2H, (ias[0][4] << 8)
851 		EMAC_WRITE(ETH_SA3L, (ias[1][3] << 24)
854 		EMAC_WRITE(ETH_SA3H, (ias[1][4] << 8)
862 		EMAC_WRITE(ETH_SA3L, (ias[2][3] << 24)
865 		EMAC_WRITE(ETH_SA3H, (ias[2][4] << 8)
868 	EMAC_WRITE(ETH_HSH, hashes[0]);
869 	EMAC_WRITE(ETH_HSL, hashes[1]);
870 	EMAC_WRITE(ETH_CFG, cfg);
871 	EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);