arc/jazz/fdc_jazzio.c

155 	struct fdc_jazzio_softc *jsc = device_private(self);
156 	struct fdc_softc *fdc = &jsc->sc_fdc;
167 	jsc->sc_dmat = ja->ja_dmat;
170 	    FDC_OFFSET + FDC_NPORT, 0, &jsc->sc_baseioh)) {
175 	if (bus_space_subregion(fdc->sc_iot, jsc->sc_baseioh,
182 	    R4030_DMA_RANGE, 0, &jsc->sc_dmaioh)) {
187 	if (bus_dmamap_create(jsc->sc_dmat, MAXPHYS, 1, MAXPHYS, 0,
188 	    BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &jsc->sc_dmamap)) {
201 	bus_space_unmap(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_RANGE);
203 	bus_space_unmap(fdc->sc_iot, jsc->sc_baseioh, FDC_OFFSET + FDC_NPORT);
210 	struct fdc_jazzio_softc *jsc = (struct fdc_jazzio_softc *)fdc;
213 	bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_ENAB, 0);
214 	bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_MODE, 0);
216 	jsc->sc_datain = datain;
218 	bus_dmamap_load(jsc->sc_dmat, jsc->sc_dmamap, addr, size, NULL,
221 	bus_dmamap_sync(jsc->sc_dmat, jsc->sc_dmamap,
222 	    0, jsc->sc_dmamap->dm_mapsize,
226 	bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh,
227 	    R4030_DMA_ADDR, jsc->sc_dmamap->dm_segs[0].ds_addr);
228 	bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh,
229 	    R4030_DMA_COUNT, jsc->sc_dmamap->dm_segs[0].ds_len);
230 	bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh,
234 	bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh,
242 	struct fdc_jazzio_softc *jsc = (struct fdc_jazzio_softc *)fdc;
245 	bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_ENAB, 0);
246 	bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_MODE, 0);
252 	struct fdc_jazzio_softc *jsc = (struct fdc_jazzio_softc *)fdc;
255 	bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_COUNT, 0);
256 	bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_ENAB, 0);
257 	bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_MODE, 0);
259 	bus_dmamap_sync(jsc->sc_dmat, jsc->sc_dmamap,
260 	    0, jsc->sc_dmamap->dm_mapsize,
261 	    jsc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
262 	bus_dmamap_unload(jsc->sc_dmat, jsc->sc_dmamap);