amiga/dev/sbic.c

188 	csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \
199 	u_char csr;
214 	sbic_trace[sbic_traceptr].csr = csr_traceptr; \
227 	int csr;
701 	int csr;
710 			GET_SBIC_csr(regs, csr);
711 			printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n",
712 			    line, val, csr);
729 	u_char csr, asr;
732 	GET_SBIC_csr(regs, csr);
734 	printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n",
735 	    device_xname(dev->sc_dev), where, csr, asr);
782 			GET_SBIC_csr (regs, csr);
783 			CSR_TRACE('a',csr,asr,0);
784 		} while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1)
785 		    && (csr != SBIC_CSR_CMD_INVALID));
855 	u_char csr;
884 	GET_SBIC_csr(regs, csr);       /* clears interrupt also */
885 	__USE(csr);
944 sbicerror(struct sbic_softc *dev, sbic_regmap_t regs, u_char csr)
958 	printf("csr == 0x%02x\n", csr);	/* XXX */
968 	u_char asr, csr, id;
1025 		GET_SBIC_csr (regs, csr);
1026 		CSR_TRACE('s',csr,asr,target);
1027 		QPRINTF(("%02x ", csr));
1028 		if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) {
1034 			sbicnextstate(dev, csr, asr);
1038 		if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) {
1042 	} while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE)
1043 	    && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO);
1051 	if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) {
1060 	} else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) {
1129 		GET_SBIC_csr (regs, csr);
1130 		CSR_TRACE('y',csr,asr,target);
1131 		QPRINTF(("[%02x]", csr));
1134 			printf("csr-result of last msgout: 0x%x\n", csr);
1137 		if (csr != SBIC_CSR_SEL_TIMEO)
1140 	if (csr == SBIC_CSR_SEL_TIMEO)
1146 	return(csr == SBIC_CSR_SEL_TIMEO);
1224 	 * this leaves with one csr to be read
1234 	u_char orig_csr, csr, asr;
1250 	QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr));
1281 				GET_SBIC_csr(regs, csr);
1282 				__USE(csr);
1283 				CSR_TRACE('<',csr,asr,len);
1284 				QPRINTF(("[CSR%02xASR%02x]", csr, asr));
1292 /*		QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/
1300 	/* this leaves with one csr to be read */
1318 	u_char phase, csr, asr;
1379 		GET_SBIC_csr (regs, csr);
1380 		CSR_TRACE('I',csr,asr,target);
1381 		QPRINTF((">ASR:%02xCSR:%02x<", asr, csr));
1384 		csrbuf[bufptr++] = csr;
1388 		switch (csr) {
1416 			GET_SBIC_csr(regs, csr); /* Lets us reload tcount */
1419 			CSR_TRACE('I',csr,asr,target);
1421 				printf("next: cmd sent asr %02x, csr %02x\n",
1422 				       asr, csr);
1441 					  SBIC_PHASE(csr), wait))
1442 			    if (csr & 0x01)
1451 					     SBIC_PHASE(csr));
1485 			i = sbicnextstate(dev, csr, asr);
1498 				       csr,asr);
1528 	GET_SBIC_csr(regs, csr);
1529 	CSR_TRACE('I',csr,asr,0xff);
1561 	u_char phase, asr, csr;
1578 		GET_SBIC_csr (regs, csr);
1579 		CSR_TRACE('f',csr,asr,target);
1580 		QPRINTF(("%02x:", csr));
1581 	} while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1)
1582 	    && (csr != SBIC_CSR_S_XFERRED));
1591 		sbicerror(dev, regs, csr);
1606 	u_char csr, asr, *addr;
1772 	 * Hmm - this isn't right:  asr and csr haven't been set yet.
1775 	debug_csr = csr;
1785 		GET_SBIC_csr(regs, csr);
1786 		CSR_TRACE('g',csr,asr,dev->target);
1788 		debug_csr = csr;
1791 		QPRINTF(("go[0x%x]", csr));
1793 		i = sbicnextstate(dev, csr, asr);
1800 		if (asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n",
1801 					      asr,csr);
1805 	CSR_TRACE('g',csr,asr,i<<4);
1821 	u_char asr, csr;
1835 		GET_SBIC_csr(regs, csr);
1836 		CSR_TRACE('i',csr,asr,dev->target);
1838 		debug_csr = csr;
1841 		QPRINTF(("intr[0x%x]", csr));
1843 		i = sbicnextstate(dev, csr, asr);
1851 		if (asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n",
1852 					      asr,csr);
1856 	CSR_TRACE('i',csr,asr,i<<4);
1868 	u_char asr, csr;
1879 		GET_SBIC_csr(regs, csr);
1880 		CSR_TRACE('p',csr,asr,dev->target);
1882 		debug_csr = csr;
1885 		QPRINTF(("poll[0x%x]", csr));
1887 		i = sbicnextstate(dev, csr, asr);
1895 				       csr,asr);
1910 		if (asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n",
1911 					      asr,csr);
1915 	CSR_TRACE('p',csr,asr,i<<4);
1929 	u_char asr, csr, *tmpaddr;
1944 	GET_SBIC_selid (regs, csr);
1945 	SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI);
1953 			GET_SBIC_csr(regs, csr);
1954 			QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n",
1955 				 csr, asr));
1958 			CSR_TRACE('m',csr,asr,*tmpaddr);
1965 			GET_SBIC_csr(regs, csr);
1966 			CSR_TRACE('X',csr,asr,dev->target);
1971 				csr = 0xff;
1972 				GET_SBIC_csr(regs, csr);
1973 				CSR_TRACE('X',csr,asr,dev->target);
1974 				if (csr == 0xff)
1975 					printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr);
1976 			} while (csr == 0xff);
1980 				printf("sbicmsgin: got %02x csr %02x asr %02x\n",
1981 				       *tmpaddr, csr, asr);
1999 				while ((csr & 0x07) != MESG_OUT_PHASE) {
2005 					GET_SBIC_csr(regs, csr);
2006 					CSR_TRACE('e',csr,asr,dev->target);
2007 					if ((csr & 0x07) != MESG_OUT_PHASE) {
2008 						sbicnextstate(dev, csr, asr);
2025 				GET_SBIC_csr(regs, csr);
2026 				CSR_TRACE('X',csr,asr,dev->target);
2027 				QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n",
2028 					 csr, asr));
2041 			printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n",
2042 			       csr, asr, dev->sc_msg[0]);
2130 			GET_SBIC_csr(regs, csr);
2131 			QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr));
2133 			CSR_TRACE('x',csr,asr,*tmpaddr);
2137 			QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n",
2138 			       asr, csr, recvlen));
2167 		GET_SBIC_csr(regs, csr);
2168 		CSR_TRACE('X',csr,asr,dev->target);
2169 		QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n",
2170 			 csr, asr, recvlen));
2175 	while ((csr == SBIC_CSR_MSGIN_W_ACK)
2176 	      || (SBIC_PHASE(csr) == MESG_IN_PHASE));
2181 	QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr));
2197 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr)
2211 	QPRINTF(("next[%02x,%02x]",asr,csr));
2213 	switch (csr) {
2288 				printf("sbicnextstate:xfer count %d asr%x csr%x\n",
2289 				       acb->sc_kv.dc_count, asr, csr);
2295 					SBIC_PHASE(csr), wait)) {
2296 				if (SBIC_PHASE(csr) == DATA_IN_PHASE)
2305 						    SBIC_PHASE(csr));
2312 				printf("sbicnextstate:xfer count %d asr%x csr%x\n",
2313 				       acb->sc_kv.dc_count, asr, csr);
2357 		printf("Acking unknown msgin CSR:%02x",csr);
2411 		if (csr == SBIC_CSR_RSLT_IFY) {
2416 			CSR_TRACE('r',csr,asr,newtarget);
2432 				GET_SBIC_csr(regs,csr);
2433 				CSR_TRACE('n',csr,asr,newtarget);
2434 				if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) ||
2435 				    csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) ||
2436 				    csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) {
2441 					    csr);
2446 		if (reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI))
2448 			    csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY",
2456 				    csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY");
2488 			    csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget,
2492 		if (csr == SBIC_CSR_RSLT_IFY)
2501 		printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr);
2513 		sbicerror(dev, regs, csr);
2621 	u_char csr, asr;
2624 	GET_SBIC_csr(debug_sbic_regs,csr);
2625 	printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n",
2630 	       debug_asr, debug_csr, asr, csr);
2688 	u_char csr, asr;
2696 	printf("csr trace: ");
2700 		    csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn);
2731 		switch(csr_trace[i].csr) {
2756 			switch(csr_trace[i].csr & 0xf0) {
2766 			switch(csr_trace[i].csr & 7) {
2799 		GET_SBIC_csr(regs, csr);
2801 		csr = 0;
2802 	printf("%s@%p regs %p/%p asr %x csr %x\n", device_xname(dev->sc_dev),
2803 	    dev, regs.sbic_asr_p, regs.sbic_value_p, asr, csr);