acorn32/podulebus/sbic.c

100  * The UPROTECTED_CSR code is bogus.  It can read the csr (SCSI Status
212 	csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \
221 	u_char csr;
236 	sbic_trace[sbic_traceptr].csr = csr_traceptr; \
246 	int csr;
612 	int csr;
621 			GET_SBIC_csr(regs, csr);
622 			printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n",
623 			    line, val, csr);
640 	u_char csr, asr;
643 	GET_SBIC_csr(regs, csr);
645 	printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n",
646 	    device_xname(dev->sc_dev), where, csr, asr);
697 			GET_SBIC_csr (regs, csr);
698 			CSR_TRACE('a',csr,asr,0);
699 		} while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1)
700 		    && (csr != SBIC_CSR_CMD_INVALID));
719 /*	u_char csr;*/
785 	u_char csr;
823 	GET_SBIC_csr(regs, csr);       /* clears interrupt also */
883 sbicerror(struct sbic_softc *dev, sbic_regmap_p regs, u_char csr)
893 	printf("csr == 0x%02x\n", csr);	/* XXX */
903 	u_char asr, csr, id;
960 		GET_SBIC_csr (regs, csr);
961 		CSR_TRACE('s',csr,asr,target);
962 		QPRINTF(("%02x ", csr));
963 		if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) {
970 			sbicnextstate(dev, csr, asr);
974 		if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) {
978 	} while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
979 	    csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
980 	    csr != SBIC_CSR_SEL_TIMEO);
988 	if (csr == (SBIC_CSR_MIS_2 | CMD_PHASE)) {
997 	} else if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
1063 		GET_SBIC_csr (regs, csr);
1064 		CSR_TRACE('y',csr,asr,target);
1065 		QPRINTF(("[%02x]", csr));
1067 		DBGPRINTF(("csr-result of last msgout: 0x%x\n", csr),
1070 		if (csr != SBIC_CSR_SEL_TIMEO)
1073 	if (csr == SBIC_CSR_SEL_TIMEO)
1079 	return csr == SBIC_CSR_SEL_TIMEO;
1118 /*	u_char csr;*/
1161 	 * this leaves with one csr to be read
1174 	u_char orig_csr, csr;
1186 	QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr));
1215 				GET_SBIC_csr(regs, csr);
1216 				CSR_TRACE('<',csr,asr,len);
1217 				QPRINTF(("[CSR%02xASR%02x]", csr, asr));
1226 /*		QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/
1234 	/* this leaves with one csr to be read */
1251 	u_char phase, csr, asr;
1315 		GET_SBIC_csr (regs, csr);
1316 		CSR_TRACE('I',csr,asr,target);
1317 		QPRINTF((">ASR:%02xCSR:%02x<", asr, csr));
1320 		csrbuf[bufptr++] = csr;
1324 		switch (csr) {
1352 			GET_SBIC_csr(regs, csr); /* Lets us reload tcount */
1355 			CSR_TRACE('I',csr,asr,target);
1357 				printf("next: cmd sent asr %02x, csr %02x\n",
1358 				    asr, csr);
1376 					  SBIC_PHASE(csr), wait))
1377 			    if (csr & 0x01)
1382 				  SBIC_PHASE(csr));
1413 			i = sbicnextstate(dev, csr, asr);
1427 				    csr, asr);
1457 	GET_SBIC_csr(regs, csr);
1458 	CSR_TRACE('I',csr,asr,0xff);
1488 	u_char phase, asr, csr;
1504 		GET_SBIC_csr (regs, csr);
1505 		CSR_TRACE('f',csr,asr,target);
1506 		QPRINTF(("%02x:", csr));
1507 	} while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1)
1508 	    && (csr != SBIC_CSR_S_XFERRED));
1517 		sbicerror(dev, regs, csr);
1535 	u_char asr = 0, csr = 0;
1604 	DBG(debug_csr = csr);
1612 		GET_SBIC_csr(regs, csr);
1613 		CSR_TRACE('g', csr, asr, dev->target);
1615 		DBG(debug_csr = csr);
1618 		QPRINTF(("go[0x%x]", csr));
1620 		i = sbicnextstate(dev, csr, asr);
1628 			printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr);
1632 	CSR_TRACE('g',csr,asr,i<<4);
1649 	u_char asr, csr;
1667 		GET_SBIC_csr(regs, csr);
1668 		CSR_TRACE('i',csr,asr,dev->target);
1670 		DBG(debug_csr = csr);
1673 		QPRINTF(("intr[0x%x]", csr));
1675 		i = sbicnextstate(dev, csr, asr);
1684 			printf("sbicintr: LCI asr:%02x csr:%02x\n", asr, csr);
1688 	CSR_TRACE('i', csr, asr, i << 4);
1700 	u_char asr, csr;
1713 		GET_SBIC_csr(regs, csr);
1714 		CSR_TRACE('p', csr, asr, dev->target);
1716 		DBG(debug_csr = csr);
1719 		QPRINTF(("poll[0x%x]", csr));
1721 		i = sbicnextstate(dev, csr, asr);
1730 				    csr, asr);
1746 			printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr, csr);
1750 	CSR_TRACE('p', csr, asr, i << 4);
1764 	u_char asr, csr, *tmpaddr;
1777 	GET_SBIC_selid (regs, csr);
1778 	SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI);
1786 			GET_SBIC_csr(regs, csr);
1787 			QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n",
1788 				 csr, asr));
1791 			CSR_TRACE('m', csr, asr, *tmpaddr);
1798 			GET_SBIC_csr(regs, csr);
1799 			CSR_TRACE('X', csr, asr, dev->target);
1804 				csr = 0xff;
1805 				GET_SBIC_csr(regs, csr);
1806 				CSR_TRACE('X', csr, asr, dev->target);
1807 				if (csr == 0xff)
1808 					printf("sbicmsgin waiting: csr %02x "
1809 					    "asr %02x\n", csr, asr);
1810 			} while (csr == 0xff);
1813 			DBGPRINTF(("sbicmsgin: got %02x csr %02x asr %02x\n",
1814 			    *tmpaddr, csr, asr), reselect_debug > 1);
1833 				while ((csr & 0x07) != MESG_OUT_PHASE) {
1840 					GET_SBIC_csr(regs, csr);
1841 					CSR_TRACE('e', csr, asr, dev->target);
1842 					if ((csr & 0x07) != MESG_OUT_PHASE) {
1843 						sbicnextstate(dev, csr, asr);
1858 				GET_SBIC_csr(regs, csr);
1859 				CSR_TRACE('X',csr,asr,dev->target);
1860 				QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n",
1861 					 csr, asr));
1873 		DBGPRINTF(("msgin done csr 0x%x asr 0x%x msg 0x%x\n",
1874 		    csr, asr, dev->sc_msg[0]), sync_debug);
1958 			GET_SBIC_csr(regs, csr);
1959 			QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr));
1961 			CSR_TRACE('x',csr,asr,*tmpaddr);
1965 			QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n",
1966 			       asr, csr, recvlen));
1995 		GET_SBIC_csr(regs, csr);
1996 		CSR_TRACE('X',csr,asr,dev->target);
1997 		QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n",
1998 			 csr, asr, recvlen));
2003 	while ((csr == SBIC_CSR_MSGIN_W_ACK) ||
2004 	    (SBIC_PHASE(csr) == MESG_IN_PHASE));
2009 	QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr));
2025 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr)
2037 	QPRINTF(("next[%02x,%02x]",asr,csr));
2039 	switch (csr) {
2090 				printf("sbicnextstate:xfer count %d asr%x csr%x\n",
2091 				    acb->datalen, asr, csr);
2096 			    SBIC_PHASE(csr), wait)) {
2097 				if (SBIC_PHASE(csr) == DATA_IN_PHASE)
2103 					    acb->data, SBIC_PHASE(csr));
2121 				printf("sbicnextstate:xfer offset %d asr%x csr%x\n",
2122 				    acb->offset, asr, csr);
2151 		printf("Acking unknown msgin CSR:%02x",csr);
2200 		if (csr == SBIC_CSR_RSLT_IFY) {
2205 			CSR_TRACE('r',csr,asr,newtarget);
2221 				GET_SBIC_csr(regs,csr);
2222 				CSR_TRACE('n',csr,asr,newtarget);
2223 				if ((csr == (SBIC_CSR_MIS | MESG_IN_PHASE)) ||
2224 				    (csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE)) ||
2225 				    (csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE))) {
2230 					    csr);
2236 		    csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY",
2239 		    (reselect_debug && csr == SBIC_CSR_RSLT_NI));
2244 			    csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"),
2277 			    csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget,
2281 		if (csr == SBIC_CSR_RSLT_IFY)
2290 		printf("sbicnextstate: aborting csr %02x asr %02x\n", csr,
2303 		sbicerror(dev, regs, csr);
2360 	u_char csr, asr;
2363 	GET_SBIC_csr(debug_sbic_regs,csr);
2364 	printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n",
2369 	    debug_asr, debug_csr, asr, csr);
2425 	u_char csr, asr;
2433 	printf("csr trace: ");
2437 		    csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn);
2468 		switch(csr_trace[i].csr) {
2493 			switch(csr_trace[i].csr & 0xf0) {
2503 			switch(csr_trace[i].csr & 7) {
2536 		GET_SBIC_csr(regs, csr);
2538 		csr = 0;
2539 	printf("%s@%p regs %p asr %x csr %x\n", device_xname(dev->sc_dev),
2540 	    dev, regs, asr, csr);