sim/riscv/sim-main.c

78 fetch_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg)
81   switch (csr)
95 store_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg,
98   switch (csr)
104       cpu->csr.fcsr = (cpu->csr.fcsr & ~0xe0) | (val << 5);
109       cpu->csr.fcsr = (cpu->csr.fcsr & ~0x1f) | val;
114       cpu->csr.frm = (val >> 5) & 0x7;
115       cpu->csr.fflags = val & 0x1f;
158   unsigned int csr = (iw >> OP_SH_CSR) & OP_MASK_CSR;
511       switch (csr)
515 	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
516 	  store_csr (cpu, #name, num, &cpu->csr.name, \
517 		     cpu->csr.name & !cpu->regs[rs1]); \
525       switch (csr)
529 	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
530 	  store_csr (cpu, #name, num, &cpu->csr.name, \
531 		     cpu->csr.name | cpu->regs[rs1]); \
539       switch (csr)
543 	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
544 	  store_csr (cpu, #name, num, &cpu->csr.name, cpu->regs[rs1]); \
553       store_rd (cpu, rd, fetch_csr (cpu, "cycle", CSR_CYCLE, &cpu->csr.cycle));
559 		fetch_csr (cpu, "cycleh", CSR_CYCLEH, &cpu->csr.cycleh));
564 		fetch_csr (cpu, "instret", CSR_INSTRET, &cpu->csr.instret));
570 		fetch_csr (cpu, "instreth", CSR_INSTRETH, &cpu->csr.instreth));
574       store_rd (cpu, rd, fetch_csr (cpu, "time", CSR_TIME, &cpu->csr.time));
579       store_rd (cpu, rd, fetch_csr (cpu, "timeh", CSR_TIMEH, &cpu->csr.timeh));
1005   ++cpu->csr.cycle;
1006   ++cpu->csr.instret;
1049       memcpy (buf, &cpu->csr.name, len); \
1082       memcpy (&cpu->csr.name, buf, len); \
1117   cpu->csr.misa = 0;
1120     cpu->csr.misa |= (uint64_t)2 << 62;
1133 	    cpu->csr.misa |= 0x1129;  /* G = IMAFD.  */
1135 	    cpu->csr.misa |= (1 << i);
1139   cpu->csr.mimpid = 0x8000;
1140   cpu->csr.mhartid = mhartid;