Lines Matching defs:level
41 That is, it implements edge- rather than level-triggered
56 16: ILR0: interrupt level register 3..0
57 20: ILR1: interrupt level register 7..4
58 24: ILR2: interrupt level register 11..8
59 28: ILR3: interrupt level register 15..12
70 associated with the event is the interrupt level (16-31), as given
75 An output level of zero signals the clearing of a level interrupt.
80 External interrupts. Level = 0 -> level interrupt cleared.
85 DMA internal interrupts, correspond to DMA channels 0-3. Level = 0 -> level interrupt cleared.
90 SIO internal interrupts. Level = 0 -> level interrupt cleared.
95 Timer internal interrupts. Level = 0 -> level interrupt cleared.
142 /* in increasing order of level number */
262 int level)
267 if (level == 0)
296 HW_TRACE ((me, "interrupt level %d", ILR_GET(controller, source)));