Lines Matching refs:regno
65 crisv10f_h_gr_get (SIM_CPU *current_cpu, UINT regno)
67 return GET_H_GR (regno);
73 crisv10f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
75 SET_H_GR (regno, newval);
81 crisv10f_h_gr_pc_get (SIM_CPU *current_cpu, UINT regno)
83 return GET_H_GR_PC (regno);
89 crisv10f_h_gr_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
91 SET_H_GR_PC (regno, newval);
97 crisv10f_h_gr_real_pc_get (SIM_CPU *current_cpu, UINT regno)
99 return CPU (h_gr_real_pc[regno]);
105 crisv10f_h_gr_real_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
107 CPU (h_gr_real_pc[regno]) = newval;
113 crisv10f_h_raw_gr_pc_get (SIM_CPU *current_cpu, UINT regno)
115 return GET_H_RAW_GR_PC (regno);
121 crisv10f_h_raw_gr_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
123 SET_H_RAW_GR_PC (regno, newval);
129 crisv10f_h_sr_get (SIM_CPU *current_cpu, UINT regno)
131 return GET_H_SR (regno);
137 crisv10f_h_sr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
139 SET_H_SR (regno, newval);
145 crisv10f_h_sr_v10_get (SIM_CPU *current_cpu, UINT regno)
147 return GET_H_SR_V10 (regno);
153 crisv10f_h_sr_v10_set (SIM_CPU *current_cpu, UINT regno, SI newval)
155 SET_H_SR_V10 (regno, newval);