Lines Matching refs:REST
232 #define REST 0,0,ZPAR
235 { "???", 1,0,0,0x0000, 0x0000, {0}, 0, REST};
238 { "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
239 { "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
240 { "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
241 { "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
243 { "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
244 { "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
245 { "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
246 { "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
247 { "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
248 { "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
249 { "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
250 { "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST},/*PREFER*/
253 { "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
254 { "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, 0, REST},
255 { "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
256 { "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
257 { "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
258 { "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
259 { "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},
260 { "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST },
261 { "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
262 { "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
263 { "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, REST},
264 { "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
265 { "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
266 { "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
267 { "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
268 { "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, REST},
269 { "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, REST},
271 B_BRANCH|FL_NR, REST},
273 B_BRANCH|FL_DELAY|FL_NR, REST},
274 { "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, 0, REST},
275 { "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
276 { "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR, REST},
277 { "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
278 { "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
279 { "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
280 { "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
282 B_BRANCH|FL_NR, REST},
284 B_BRANCH|FL_DELAY|FL_NR, REST},
285 { "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
286 { "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
287 { "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, REST},
288 { "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
289 { "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, 0, REST},
290 { "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
291 { "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR, REST},
292 { "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
293 { "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
294 { "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
295 { "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, REST},
296 { "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
297 { "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
298 { "estop", 1,0,0,0xF4F0, 0xFFFF, {OP_None}, 0, REST}, /* undocumented */
299 { "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, 0, REST},
300 { "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
301 { "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
302 { "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
303 { "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
304 { "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, 0, REST},
305 { "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, 0, REST},
306 { "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
307 { "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
308 { "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
309 { "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
310 { "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, REST},
311 { "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
312 { "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
313 { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, 0, REST},/*SRC*/
315 { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
316 { "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, 0, REST},/*SRC*/
317 { "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, 0, REST},/*SRC*/
318 { "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, REST},/*SRC*/
319 { "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, REST},/*PREFER */
320 { "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR, REST},/*SRC*/
321 { "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR, REST},/*SRC*/
322 { "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR, REST},/*SRC*/
323 { "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
324 { "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR, REST},
325 { "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR, REST},
326 { "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, 0, REST},/*PREFER*/
329 { "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, 0, REST},
330 { "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, 0, REST},
331 { "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, 0, REST},
332 { "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
333 { "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
334 { "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR, REST},/*pseudo-op*/
335 { "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
336 { "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR, REST},
337 { "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
338 { "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
339 { "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, 0, REST},
340 { "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
341 { "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
342 { "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR, REST},
343 { "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
344 { "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
345 { "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
346 { "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
347 { "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
348 { "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
349 { "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, 0, REST},
350 { "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, 0, REST},
351 { "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
352 { "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
353 { "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
354 { "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
355 { "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},/*SRC*/
356 { "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
357 { "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},
358 { "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, 0, REST},
359 { "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, 0, REST},
360 { "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
361 { "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
362 { "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR, REST},
363 { "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, 0, REST},
364 { "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
365 { "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, 0, REST}, /*SRC*/
366 { "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR, REST},
367 { "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
368 { "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
369 { "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR, REST},
370 { "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, 0, REST},
371 { "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR, REST},
372 { "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, 0, REST},
373 { "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, 0, REST},
374 { "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, REST},
375 { "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, 0, REST},
376 { "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
377 { "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, 0, REST},
378 { "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
379 { "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
380 { "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
381 { "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
382 { "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
383 { "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
384 { "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR, REST},
385 { "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, 0, REST},
386 { "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, 0, REST},
387 { "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, 0, REST},
388 { "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR, REST},
389 { "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR, REST},
390 { "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, 0, REST},
391 { "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
392 { "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
394 B_RET|FL_NR, REST},
396 B_RET|FL_DELAY|FL_NR, REST},
397 { "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, 0, REST},
398 { "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, REST},
399 { "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
400 { "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
401 { "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
402 { "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
403 { "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR, REST},
404 { "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, 0, REST},
405 { "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, 0, REST},
406 { "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, 0, REST},
407 { "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, REST},
408 { "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, REST},
409 { "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, REST},
410 { "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, REST},
411 { "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, REST},
412 { "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, REST},
413 { "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
414 { "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, 0, REST},
415 { "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, 0, REST},
416 { "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
417 { "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, 0, REST},
418 { "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
419 { "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
420 { "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, 0, REST},/*SRC*/
421 { "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
422 { "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
423 { "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
424 { "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
425 { "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
426 { "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, 0, REST},
427 { "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, 0, REST},
428 { "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, 0, REST},
429 { "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
430 { "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
431 { "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
434 { "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
435 { "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
436 { "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
439 { "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, 0, REST},
440 { "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, 0, REST},
441 { "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
442 { "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
443 { "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
444 { "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
445 { "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
446 { "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
447 { "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST}, /*PREFER*/
450 { "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
451 { "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
452 { "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
453 { "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
454 { "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
455 { "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
456 { "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
457 { "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR, REST},
458 { "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, REST},
459 { "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
460 { "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
461 { "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
462 { "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
463 { "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, REST},
464 { NULL, 0,0,0,0,0, {}, 0, REST},
495 { NULL, 0, 0, 0, 0, 0, {0,0,0,0}, 0, REST },