dist/opcodes/s390-opc.c

158 #define D_20        42            /* Displacement starting at position 20 */
329 #define INSTR_RIS_RURDI    6, { R_8,I8_32,U4_12,D_20,B_16,0 }    /* e.g. cib   */
330 #define INSTR_RIS_R0RDI    6, { R_8,I8_32,D_20,B_16,0,0 }        /* e.g. cibne */
331 #define INSTR_RIS_RURDU    6, { R_8,U8_32,U4_12,D_20,B_16,0 }    /* e.g. clib  */
332 #define INSTR_RIS_R0RDU    6, { R_8,U8_32,D_20,B_16,0,0 }        /* e.g. clibne*/
400 #define INSTR_RRS_RRRDU    6, { R_8,R_12,U4_32,D_20,B_16 }       /* e.g. crb   */
401 #define INSTR_RRS_RRRD0    6, { R_8,R_12,D_20,B_16,0 }           /* e.g. crbne */
402 #define INSTR_RSE_RRRD     6, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. lmh   */
403 #define INSTR_RSE_RERERD   6, { RE_8,RE_12,D_20,B_16,0,0 }       /* e.g. mvclu */
404 #define INSTR_RSE_CCRD     6, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. stctg */
405 #define INSTR_RSE_RURD     6, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icmh  */
406 #define INSTR_RSL_R0RD     6, { D_20,L4_8,B_16,0,0,0 }           /* e.g. tp    */
407 #define INSTR_RSL_LRDFU    6, { F_32,D_20,L8_8,B_16,U4_36,0 }    /* e.g. cdzt  */
408 #define INSTR_RSL_LRDFEU   6, { FE_32,D_20,L8_8,B_16,U4_36,0 }   /* e.g. cxzt  */
417 #define INSTR_RS_AARD      4, { A_8,A_12,D_20,B_16,0,0 }         /* e.g. lam   */
418 #define INSTR_RS_CCRD      4, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lctl  */
419 #define INSTR_RS_R0RD      4, { R_8,D_20,B_16,0,0,0 }            /* e.g. sll   */
420 #define INSTR_RS_RE0RD     4, { RE_8,D_20,B_16,0,0,0 }           /* e.g. slda  */
421 #define INSTR_RS_RRRD      4, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. cs    */
422 #define INSTR_RS_RERERD    4, { RE_8,RE_12,D_20,B_16,0,0 }       /* e.g. cds   */
423 #define INSTR_RS_RURD      4, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icm   */
424 #define INSTR_RXE_FRRD     6, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. adb   */
425 #define INSTR_RXE_FERRD    6, { FE_8,D_20,X_12,B_16,0,0 }        /* e.g. lxdb  */
426 #define INSTR_RXE_RRRD     6, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. lg    */
427 #define INSTR_RXE_RRRDU    6, { R_8,D_20,X_12,B_16,U4_32,0 }     /* e.g. lcbb  */
428 #define INSTR_RXE_RERRD    6, { RE_8,D_20,X_12,B_16,0,0 }        /* e.g. dsg   */
429 #define INSTR_RXF_FRRDF    6, { F_32,F_8,D_20,X_12,B_16,0 }      /* e.g. madb  */
430 #define INSTR_RXF_FRRDFE   6, { FE_32,F_8,D_20,X_12,B_16,0 }     /* e.g. my    */
431 #define INSTR_RXF_FERRDFE  6, { FE_32,FE_8,D_20,X_12,B_16,0 }    /* e.g. slxt  */
432 #define INSTR_RXF_RRRDR    6, { R_32,R_8,D_20,X_12,B_16,0 }      /* e.g. .insn */
438 #define INSTR_RX_0RRD      4, { D_20,X_12,B_16,0,0,0 }           /* e.g. be    */
439 #define INSTR_RX_FRRD      4, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. ae    */
440 #define INSTR_RX_FERRD     4, { FE_8,D_20,X_12,B_16,0,0 }        /* e.g. mxd   */
441 #define INSTR_RX_RRRD      4, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. l     */
442 #define INSTR_RX_RERRD     4, { RE_8,D_20,X_12,B_16,0,0 }        /* e.g. d     */
443 #define INSTR_RX_URRD      4, { U4_8,D_20,X_12,B_16,0,0 }        /* e.g. bc    */
444 #define INSTR_SI_RD        4, { D_20,B_16,0,0,0,0 }              /* e.g. lpsw  */
445 #define INSTR_SI_URD       4, { D_20,B_16,U8_8,0,0,0 }           /* e.g. cli   */
449 #define INSTR_SIL_RDI      6, { D_20,B_16,I16_32,0,0,0 }         /* e.g. chhsi */
450 #define INSTR_SIL_RDU      6, { D_20,B_16,U16_32,0,0,0 }         /* e.g. clfhsi */
451 #define INSTR_SMI_U0RDP    6, { U4_8,J16_32,D_20,B_16,0,0 }      /* e.g. bpp   */
452 #define INSTR_SSE_RDRD     6, { D_20,B_16,D_36,B_32,0,0 }        /* e.g. mvcdk */
453 #define INSTR_SS_L0RDRD    6, { D_20,L8_8,B_16,D_36,B_32,0     } /* e.g. mvc   */
454 #define INSTR_SS_L2RDRD    6, { D_20,B_16,D_36,L8_8,B_32,0     } /* e.g. pka   */
455 #define INSTR_SS_LIRDRD    6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp   */
456 #define INSTR_SS_LLRDRD    6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack  */
457 #define INSTR_SS_RRRDRD    6, { D_20,R_8,B_16,D_36,B_32,R_12 }   /* e.g. mvck  */
458 #define INSTR_SS_RRRDRD2   6, { R_8,D_20,B_16,R_12,D_36,B_32 }   /* e.g. plo   */
459 #define INSTR_SS_RRRDRD3   6, { R_8,R_12,D_20,B_16,D_36,B_32 }   /* e.g. lmd   */
460 #define INSTR_SSF_RRDRD    6, { D_20,B_16,D_36,B_32,R_8,0 }      /* e.g. mvcos */
461 #define INSTR_SSF_RERDRD2  6, { RE_8,D_20,B_16,D_36,B_32,0 }     /* e.g. lpd   */
463 #define INSTR_S_RD         4, { D_20,B_16,0,0,0,0 }              /* e.g. stck  */
464 #define INSTR_VRV_VVXRDU   6, { V_8,D_20,VX_12,B_16,U4_32,0 }    /* e.g. vgef  */
481 #define INSTR_VRX_VRRD     6, { V_8,D_20,X_12,B_16,0,0 }         /* e.g. vl    */
483 #define INSTR_VRX_VRRDU    6, { V_8,D_20,X_12,B_16,U4_32,0 }     /* e.g. vlrep */
484 #define INSTR_VRS_RVRDU    6, { R_8,V_12,D_20,B_16,U4_32,0 }     /* e.g. vlgv  */
485 #define INSTR_VRS_RVRD     6, { R_8,V_12,D_20,B_16,0,0 }         /* e.g. vlgvb */
486 #define INSTR_VRS_VVRDU    6, { V_8,V_12,D_20,B_16,U4_32,0 }     /* e.g. verll */
487 #define INSTR_VRS_VVRD     6, { V_8,V_12,D_20,B_16,0,0 }         /* e.g. vlm   */
488 #define INSTR_VRS_VRRDU    6, { V_8,R_12,D_20,B_16,U4_32,0 }     /* e.g. vlvg  */
489 #define INSTR_VRS_VRRD     6, { V_8,R_12,D_20,B_16,0,0 }         /* e.g. vlvgb */
490 #define INSTR_VRS_RRDV     6, { V_32,R_12,D_20,B_16,0,0 }        /* e.g. vlrlr */
523 #define INSTR_VSI_URDV     6, { V_32,D_20,B_16,U8_8,0,0 }        /* e.g. vlrl  */