Lines Matching defs:X_MASK
4012 #define P_X_MASK (PREFIX_MASK | X_MASK)
4503 #define X_MASK XRC (0x3f, 0x3ff, 1)
4506 #define XBF_MASK (X_MASK | (3 << 21))
4551 /* An X_MASK with an accumulator register and the RA and RB fields fixed. */
4552 #define XACC_MASK (X_MASK | RA_MASK | RB_MASK | (3 << 21))
4555 /* An X_MASK with two dense math register. */
4556 #define XDMRDMR_MASK (X_MASK | RA_MASK | (3 << 21) | (3 << 11))
4584 /* An X_MASK with the RA/VA field fixed. */
4585 #define XRA_MASK (X_MASK | RA_MASK)
4592 /* An X_MASK with the RB field fixed. */
4593 #define XRB_MASK (X_MASK | RB_MASK)
4595 /* An X_MASK with the RT field fixed. */
4596 #define XRT_MASK (X_MASK | RT_MASK)
4604 /* An X_MASK with the RA and RB fields fixed. */
4605 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
4616 /* An X_MASK with the RT and RA fields fixed. */
4617 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
4619 /* An X_MASK with the RT and RB fields fixed. */
4620 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
4625 /* An X_MASK with the RT, RA and RB fields fixed. */
4626 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
4674 #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22))
4684 #define XTO_MASK (X_MASK | TO_MASK)
4690 #define XTLB_MASK (X_MASK | SH_MASK)
4715 /* An X_MASK, but with the EH bit clear. */
4716 #define XEH_MASK (X_MASK & ~((uint64_t )1))
4803 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
4816 #define XSPR_MASK (X_MASK | SPR_MASK)
5045 {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
5116 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5117 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5205 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5207 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5257 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5259 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5273 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5274 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5579 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5581 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5619 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5620 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
6616 {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
7070 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
7071 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
7073 {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7074 {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7099 {"isellt", XISEL(31,15,0), X_MASK, PPCISEL, EXT, {RT, RA0, RB}},
7100 {"iselgt", XISEL(31,15,1), X_MASK, PPCISEL, EXT, {RT, RA0, RB}},
7101 {"iseleq", XISEL(31,15,2), X_MASK, PPCISEL, EXT, {RT, RA0, RB}},
7107 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
7114 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
7116 {"icbt", X(31,22), X_MASK, POWER5|BOOKE|PPCE300, 0, {CT, RA0, RB}},
7118 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
7119 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
7121 {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
7122 {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
7123 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
7124 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
7131 {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
7132 {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
7134 {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
7135 {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
7137 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
7138 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
7140 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7148 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7155 {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7156 {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7161 {"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}},
7163 {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7179 {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
7183 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
7187 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
7188 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
7193 {"cntlzdm", X(31,59), X_MASK, POWER10, 0, {RA, RS, RB}},
7195 {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
7196 {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
7219 {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
7235 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
7236 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
7251 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
7253 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7257 {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7269 {"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}},
7281 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
7285 {"not", XRC(31,124,0), X_MASK, COM, EXT, {RA, RSB}},
7286 {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
7287 {"not.", XRC(31,124,1), X_MASK, COM, EXT, {RA, RSB}},
7288 {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
7296 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7298 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7316 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
7325 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
7326 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
7328 {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
7330 {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
7332 {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
7333 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
7335 {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
7336 {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
7338 {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
7339 {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
7344 {"pdepd", X(31,156), X_MASK, POWER10, 0, {RA, RS, RB}},
7346 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7348 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7352 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7354 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7362 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
7379 {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
7381 {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
7383 {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}},
7384 {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
7386 {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
7387 {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
7389 {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
7390 {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
7395 {"pextd", X(31,188), X_MASK, POWER10, 0, {RA, RS, RB}},
7399 {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
7401 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7423 {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
7425 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
7427 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
7429 {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
7431 {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
7432 {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
7434 {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
7435 {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
7438 {"cfuged", X(31,220), X_MASK, POWER10, 0, {RA, RS, RB}},
7440 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7444 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7446 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7469 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
7479 {"dcbtstct", X(31,246), X_MASK, POWER4, EXT, {RA0, RB, THCT}},
7480 {"dcbtstds", X(31,246), X_MASK, POWER4, EXT, {RA0, RB, THDS}},
7481 {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
7482 {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
7483 {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
7485 {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
7487 {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
7488 {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
7490 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
7492 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7494 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
7495 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
7497 {"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}},
7501 {"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}},
7507 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
7514 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
7521 {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, 0, {RB, RSO, RIC, PRS, X_R}},
7524 {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
7528 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
7529 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
7533 {"dcbtct", X(31,278), X_MASK, POWER4, EXT, {RA0, RB, THCT}},
7534 {"dcbtds", X(31,278), X_MASK, POWER4, EXT, {RA0, RB, THDS}},
7535 {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
7536 {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
7537 {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
7539 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
7543 {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
7544 {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
7546 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7548 {"mfdcrux", X(31,291), X_MASK, PPC464|PPC476, 0, {RS, RA}},
7550 {"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}},
7551 {"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}},
7555 {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
7557 {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
7564 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
7566 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
7570 {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
7571 {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
7573 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7609 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
7610 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
7612 {"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}},
7614 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
7623 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
7624 {"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}},
7693 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, EXT, {RT, TBR}},
7926 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
7928 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
7933 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
7935 {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7948 {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
7951 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
7956 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
7962 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
7963 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
7965 {"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}},
7967 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7978 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
7984 {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
7986 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
7987 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
7989 {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
7991 {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
7992 {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
7994 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7998 {"mtdcrux", X(31,419), X_MASK, PPC464|PPC476, 0, {RA, RS}},
8000 {"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}},
8002 {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
8017 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
8019 {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
8043 {"mr", XRC(31,444,0), X_MASK, COM, EXT, {RA, RSB}},
8044 {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
8045 {"mr.", XRC(31,444,1), X_MASK, COM, EXT, {RA, RSB}},
8046 {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
8084 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
8085 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
8087 {"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}},
8100 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
8101 {"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}},
8362 {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
8366 {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
8367 {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
8373 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}},
8375 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
8377 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
8388 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
8397 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
8401 {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
8402 {"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
8404 {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
8406 {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
8426 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
8428 {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
8429 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
8431 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
8432 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
8434 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
8436 {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
8437 {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
8438 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
8439 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
8441 {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
8442 {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
8447 {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
8448 {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
8450 {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
8451 {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
8453 {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
8454 {"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
8456 {"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}},
8458 {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
8460 {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
8472 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
8477 {"cnttzdm", X(31,571), X_MASK, POWER10, 0, {RA, RS, RB}},
8481 {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
8482 {"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
8484 {"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}},
8486 {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
8495 {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
8496 {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
8514 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
8517 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
8519 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
8521 {"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}},
8523 {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
8535 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
8539 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
8541 {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
8542 {"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
8544 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
8566 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
8568 {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
8569 {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
8571 {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
8572 {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
8574 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
8576 {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
8577 {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
8579 {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
8580 {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
8582 {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
8583 {"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
8585 {"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}},
8587 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
8597 {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
8599 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
8601 {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
8602 {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
8604 {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
8605 {"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
8607 {"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}},
8609 {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
8630 {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
8631 {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
8633 {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
8635 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
8637 {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
8638 {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
8640 {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
8641 {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
8644 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
8646 {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
8648 {"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}},
8650 {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
8685 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
8687 {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
8688 {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
8690 {"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}},
8694 {"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}},
8695 {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
8706 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
8707 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
8712 {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
8716 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
8718 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
8720 {"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
8721 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
8723 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
8724 {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
8725 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
8726 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
8728 {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
8729 {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
8732 {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
8734 {"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}},
8735 {"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}},
8736 {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
8741 {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
8743 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
8745 {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
8747 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
8752 {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
8754 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
8755 {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
8756 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
8757 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
8762 {"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}},
8772 {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
8782 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
8785 {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
8789 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
8791 {"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}},
8801 {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
8805 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
8809 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
8817 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
8830 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
8831 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
8836 {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
8838 {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
8840 {"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
8841 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
8843 {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
8844 {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
8846 {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
8847 {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
8855 {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
8857 {"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}},
8861 {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
8863 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
8877 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
8879 {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
8881 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
8882 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
8884 {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
8886 {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
8887 {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
8892 {"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}},
8909 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
8913 {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
8917 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
8924 {"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}},
8943 {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
9019 {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9020 {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9067 {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9068 {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9098 {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
9105 {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
9129 {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9130 {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9135 {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9136 {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9138 {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
9139 {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
9149 {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9150 {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9170 {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9171 {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9173 {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9174 {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9183 {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
9185 {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
9186 {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
9195 {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9196 {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
9198 {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
9199 {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
9203 {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
9204 {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
9212 {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9213 {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9459 {"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9460 {"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9465 {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9466 {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9471 {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
9472 {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
9545 {"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9546 {"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9551 {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9552 {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9570 {"xscmpeqqp", X(63,68), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9584 {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9588 {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
9607 {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
9613 {"xscmpgeqp", X(63,196), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9620 {"xscmpgtqp", X(63,228), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9622 {"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
9623 {"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
9628 {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
9629 {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
9631 {"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
9632 {"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
9634 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
9635 {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
9637 {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9638 {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9643 {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9644 {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9649 {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9650 {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9655 {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9656 {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9661 {"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9662 {"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9664 {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9665 {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9667 {"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9668 {"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9670 {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9671 {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9683 {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
9687 {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
9688 {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
9690 {"xsmaxcqp", X(63,676), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9692 {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
9699 {"xsmincqp", X(63,740), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9701 {"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
9702 {"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
9704 {"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
9705 {"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
9725 {"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
9726 {"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
9742 {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
9749 {"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
9750 {"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
9752 {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9760 {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
10085 {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
10087 {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},