sim/m32r/model.c

377     INT in_src1 = -1;
379     in_src1 = FLD (in_src1);
383     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
406     INT in_src1 = -1;
410     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
433     INT in_src1 = -1;
437     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
460     INT in_src1 = -1;
464     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
487     INT in_src1 = -1;
491     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
514     INT in_src1 = -1;
518     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
541     INT in_src1 = -1;
545     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
640     INT in_src1 = -1;
642     in_src1 = FLD (in_src1);
646     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
698     INT in_src1 = -1;
700     in_src1 = FLD (in_src1);
704     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
720     INT in_src1 = -1;
724     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
740     INT in_src1 = -1;
742     in_src1 = FLD (in_src1);
746     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
762     INT in_src1 = -1;
766     cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1261     INT in_src1 = -1;
1263     in_src1 = FLD (in_src1);
1267     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1283     INT in_src1 = -1;
1285     in_src1 = FLD (in_src1);
1289     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1305     INT in_src1 = -1;
1307     in_src1 = FLD (in_src1);
1311     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1327     INT in_src1 = -1;
1329     in_src1 = FLD (in_src1);
1333     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1374     INT in_src1 = -1;
1376     in_src1 = FLD (in_src1);
1380     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1396     INT in_src1 = -1;
1398     in_src1 = FLD (in_src1);
1402     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1418     INT in_src1 = -1;
1420     in_src1 = FLD (in_src1);
1424     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1440     INT in_src1 = -1;
1442     in_src1 = FLD (in_src1);
1446     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1572     in_sr = FLD (in_src1);
1592     in_sr = FLD (in_src1);
1695     INT in_src1 = -1;
1697     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1713     INT in_src1 = -1;
1715     cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1984     INT in_src1 = 0;
1986     in_src1 = FLD (in_src1);
1990     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2006     INT in_src1 = 0;
2008     in_src1 = FLD (in_src1);
2012     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2028     INT in_src1 = 0;
2030     in_src1 = FLD (in_src1);
2034     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2050     INT in_src1 = 0;
2052     in_src1 = FLD (in_src1);
2056     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2072     INT in_src1 = 0;
2074     in_src1 = FLD (in_src1);
2078     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2094     INT in_src1 = 0;
2096     in_src1 = FLD (in_src1);
2100     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2116     INT in_src1 = 0;
2118     in_src1 = FLD (in_src1);
2122     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2148     INT in_src1 = 0;
2150     in_src1 = FLD (in_src1);
2154     cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);