sim/d10v/simops.c

84 	  SET_HELD_SP (PSW_SM, GPR (SP_IDX));
403 						 (uint16) GPR (OP[i]));
411 	      tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
467 						 (uint16)GPR (OP[i + 1]));
473 						 (uint16) GPR (0));
478 						 (uint16) GPR (1));
483 						 (uint16) GPR (2));
591   tmp = GPR(OP[0]);
641   uint16 a = GPR (OP[0]);
642   uint16 b = GPR (OP[1]);
655   tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
701   uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
702   uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
715   uint16 a = GPR (OP[1]);
729   tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
758   tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
810   uint16 a = GPR (OP[0]);
827   uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
837   uint16 tmp = GPR (OP[1]) & OP[2];
849   tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
880   tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
949   tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
960   SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
979   SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
999   SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
1019   SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1029   SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1039   SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1049   SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1059   SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1069   SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1155   foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1156   tmp = (int16)foo - (int16)(GPR (OP[1]));
1157   tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1159   lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1245   if (((int16)GPR (OP[1])) >= 0)
1246     tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1248     tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1298   JMP (GPR (OP[0]));
1310   JMP (GPR (OP[0]));
1319   uint16 addr = OP[1] + GPR (OP[2]);
1336   uint16 addr = GPR (OP[1]);
1355   uint16 addr = GPR (OP[1]);
1374   uint16 addr = GPR (OP[1]);
1408   uint16 addr = OP[1] + GPR (OP[2]);
1424   uint16 addr = GPR (OP[1]);
1444   uint16 addr = GPR (OP[1]);
1462   uint16 addr = GPR (OP[1]);
1498   tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1509   tmp = SEXT8 (RB (GPR (OP[1])));
1542   tmp = RB (OP[1] + GPR (OP[2]));
1553   tmp = RB (GPR (OP[1]));
1565   tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1596   tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1613   src1 = (uint16) GPR (OP[1]);
1614   src2 = (uint16) GPR (OP[2]);
1630   if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1632       tmp = GPR (OP[1]);
1637       tmp = GPR (OP[0]);
1652   tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1696   if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1698       tmp = GPR (OP[1]);
1703       tmp = GPR (OP[0]);
1718   tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1761   tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1794   tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1811   src1 = (uint16) GPR (OP[1]);
1812   src2 = (uint16) GPR (OP[2]);
1827   tmp = GPR (OP[0]) * GPR (OP[1]);
1839   tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1859   tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1877   src1 = (uint16) GPR (OP[1]);
1878   src2 = (uint16) GPR (OP[2]);
1893   tmp = GPR (OP[1]);
1926   tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1948   tmp = SEXT8 (GPR (OP[1]) & 0xff);
1961       tmp = GPR (OP[1]);
1965     tmp = GPR (OP[0]);
1977       tmp = GPR (OP[1]);
1981     tmp = GPR (OP[0]);
2036 	 | ((int64)(GPR (OP[0]) & 0xff) << 32));
2048   tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
2059   tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
2070   tmp = GPR (OP[0]);
2081   tmp = (GPR (OP[1]) & 0xff);
2092   tmp = - GPR (OP[0]);
2168   tmp = ~GPR (OP[0]);
2179   tmp = (GPR (OP[0]) | GPR (OP[1]));
2190   tmp = (GPR (OP[1]) | OP[2]);
2278   SET_RPT_C (GPR (OP[0]));
2280   if (GPR (OP[0]) == 0)
2454   reg = SEXT16 (GPR (OP[1]));
2472       tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2487       tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2510   tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2521   if ((GPR (OP[1]) & 31) <= 16)
2522     tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2525       sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2550   tmp = (GPR (OP[0]) << OP[1]);
2588   tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2599   tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2609   if ((GPR (OP[1]) & 31) <= 16)
2611       int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2617       sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2628   tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2653   tmp = (GPR (OP[0]) >>  (GPR (OP[1]) & 0xf));
2663   if ((GPR (OP[1]) & 31) <= 16)
2665       int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2671       sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2683   tmp = (GPR (OP[0]) >> OP[1]);
2709   tmp = ((GPR (OP[0]) >> 1) | tmp);
2718   uint16 addr = OP[1] + GPR (OP[2]);
2725   SW (addr, GPR (OP[0]));
2733   uint16 addr = GPR (OP[1]);
2740   SW (addr, GPR (OP[0]));
2749   uint16 addr = GPR (OP[1]) - 2;
2761   SW (addr, GPR (OP[0]));
2770   uint16 addr = GPR (OP[1]);
2777   SW (addr, GPR (OP[0]));
2786   uint16 addr = GPR (OP[1]);
2798   SW (addr, GPR (OP[0]));
2814   SW (addr, GPR (OP[0]));
2822   uint16 addr = GPR (OP[2])+ OP[1];
2829   SW (addr + 0, GPR (OP[0] + 0));
2830   SW (addr + 2, GPR (OP[0] + 1));
2838   uint16 addr = GPR (OP[1]);
2845   SW (addr + 0, GPR (OP[0] + 0));
2846   SW (addr + 2, GPR (OP[0] + 1));
2854   uint16 addr = GPR (OP[1]) - 4;
2866   SW (addr + 0, GPR (OP[0] + 0));
2867   SW (addr + 2, GPR (OP[0] + 1));
2876   uint16 addr = GPR (OP[1]);
2883   SW (addr + 0, GPR (OP[0] + 0));
2884   SW (addr + 2, GPR (OP[0] + 1));
2893   uint16 addr = GPR (OP[1]);
2905   SW (addr + 0, GPR (OP[0] + 0));
2906   SW (addr + 2, GPR (OP[0] + 1));
2922   SW (addr + 0, GPR (OP[0] + 0));
2923   SW (addr + 2, GPR (OP[0] + 1));
2932   SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2941   SB (GPR (OP[1]), GPR (OP[0]));
2958   uint16 a = GPR (OP[0]);
2959   uint16 b = GPR (OP[1]);
2976   tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
3025   a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
3026   b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
3042   tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
3067   tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
3125   tmp = ((unsigned)(unsigned16) GPR (OP[0])
3170 	  sim_io_printf (sd, " %.4x", (int) GPR (i));
3191 #define FUNC   GPR (4)	/* function number */
3192 #define PARM1  GPR (0)	/* optional parm 1 */
3193 #define PARM2  GPR (1)	/* optional parm 2 */
3194 #define PARM3  GPR (2)	/* optional parm 3 */
3195 #define PARM4  GPR (3)	/* optional parm 3 */
3448 	    sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (0));
3534   SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3544   SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3563   tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3574   tmp = (GPR (OP[1]) ^ OP[2]);