Lines Matching refs:Rd
405 ARMword Rd = ntBITS (8, 11);
413 if (Rd == 15)
422 // AND{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
440 case 0x51: // BIC{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
445 ARMword Rd = ntBITS (8, 11);
454 * ainstr |= (Rd << 12);
465 ARMword Rd = ntBITS (8, 11);
471 tASSERT (Rd != 15);
483 // LSL{S}<c>.W <Rd>,<Rm>,#<imm5>
487 // LSR{S}<c>.W <Rd>,<Rm>,#<imm>
491 // ASR{S}<c>.W <Rd>,<Rm>,#<imm>
495 // ROR{S}<c> <Rd>,<Rm>,#<imm>
505 // ORR{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
511 * ainstr |= (Rd << 12);
519 case 0x53: // MVN{S}<c>.W <Rd>,<Rm>{,<shift>}
521 ARMword Rd = ntBITS (8, 11);
534 * ainstr |= (Rd << 12);
545 ARMword Rd = ntBITS (8, 11);
551 if (Rd == 15 && S)
560 // EOR{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
566 * ainstr |= (Rd << 8);
577 case 0x58: // ADD{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
580 ARMword Rd = ntBITS (8, 11);
586 tASSERT (! (Rd == 15 && S));
594 * ainstr |= (Rd << 12);
602 case 0x5A: // ADC{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
608 * ainstr |= (ntBITS (8, 11) << 12); // Rd
615 case 0x5B: // SBC{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
618 ARMword Rd = ntBITS (8, 11);
632 * ainstr |= (Rd << 12);
640 case 0x5E: // RSB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}
641 case 0x5D: // SUB{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
644 ARMword Rd = ntBITS (8, 11);
652 if (Rd == 15)
656 Rd = 0;
665 * ainstr |= (Rd << 12);
684 ARMword Rd = ntBITS (8, 11);
691 if (Rd == 15)
698 // AND{S}<c> <Rd>,<Rn>,#<const>
702 state->Reg[Rd] = val;
715 ARMword Rd = ntBITS (8, 11);
722 state->Reg[Rd] = state->Reg[Rn] & ~ imm8;
725 ARMul_NegZero (state, state->Reg[Rd]);
731 case 0x82: // MOV{S}<c>.W <Rd>,#<const>
734 ARMword Rd = ntBITS (8, 11);
737 state->Reg[Rd] = val;
747 case 0x83: // MVN{S}<c> <Rd>,#<const>
750 ARMword Rd = ntBITS (8, 11);
754 state->Reg[Rd] = val;
766 ARMword Rd = ntBITS (8, 11);
775 if (Rd == 15 && S)
780 // EOR{S}<c> <Rd>,<Rn>,#<const>
781 state->Reg[Rd] = result;
796 ARMword Rd = ntBITS (8, 11);
804 if (Rd == 15 && S)
811 // ADD{S}<c>.W <Rd>,<Rn>,#<const>
817 state->Reg[Rd] = res;
842 case 0x8A: // ADC{S}<c> <Rd>,<Rn>,#<const>
845 ARMword Rd = ntBITS (8, 11);
858 state->Reg[Rd] = res;
884 case 0x8B: // SBC{S}<c> <Rd>,<Rn>,#<const>
887 ARMword Rd = ntBITS (8, 11);
900 state->Reg[Rd] = res;
929 ARMword Rd = ntBITS (8, 11);
936 if (Rd == 15 && S)
943 // SUB{S}<c>.W <Rd>,<Rn>,#<const>
947 state->Reg[Rd] = res;
971 case 0x8E: // RSB{S}<c>.W <Rd>,<Rn>,#<const>
974 ARMword Rd = ntBITS (8, 11);
983 state->Reg[Rd] = res;
1006 case 0x90: // ADDW<c> <Rd>,<Rn>,#<imm12>
1009 ARMword Rd = ntBITS (8, 11);
1015 state->Reg[Rd] = state->Reg[Rn] + imm12;
1021 case 0x92: // MOVW<c> <Rd>,#<imm16>
1023 ARMword Rd = ntBITS (8, 11);
1026 state->Reg[Rd] = imm;
1033 case 0x95:// SUBW<c> <Rd>,<Rn>,#<imm12>
1035 ARMword Rd = ntBITS (8, 11);
1045 state->Reg[Rd] = state->Reg[Rn] - imm12;
1052 case 0x96: // MOVT<c> <Rd>,#<imm16>
1054 ARMword Rd = ntBITS (8, 11);
1057 state->Reg[Rd] &= 0xFFFF;
1058 state->Reg[Rd] |= (imm << 16);
1063 case 0x9A: // SBFXc> <Rd>,<Rn>,#<lsb>,#<width>
1069 * ainstr |= (ntBITS (8, 11) << 12); // Rd
1077 ARMword Rd = ntBITS (8, 11);
1093 // BFC<c> <Rd>,#<lsb>,#<width>
1094 state->Reg[Rd] &= ~ mask;
1098 // BFI<c> <Rd>,<Rn>,#<lsb>,#<width>
1102 state->Reg[Rd] &= ~ mask;
1103 state->Reg[Rd] |= val;
1110 case 0x9E: // UBFXc> <Rd>,<Rn>,#<lsb>,#<width>
1116 * ainstr |= (ntBITS (8, 11) << 12); // Rd
1554 ARMword Rd = ntBITS (8, 11);
1560 // SXTH<c>.W <Rd>,<Rm>{,<rotation>}
1568 state->Reg[Rd] = val;
1572 // LSL{S}<c>.W <Rd>,<Rn>,<Rm>
1577 state->Reg[Rd] = state->Reg[Rn] << (state->Reg[Rm] & 0xFF);
1579 ARMul_NegZero (state, state->Reg[Rd]);
1585 case 0x0D1: // LSR{S}<c>.W <Rd>,<Rn>,<Rm>
1587 ARMword Rd = ntBITS (8, 11);
1594 state->Reg[Rd] = state->Reg[Rn] >> (state->Reg[Rm] & 0xFF);
1596 ARMul_NegZero (state, state->Reg[Rd]);
1606 // UXTB<c>.W <Rd>,<Rm>{,<rotation>}
1613 // ASR{S}<c>.W <Rd>,<Rn>,<Rm>
1622 * ainstr |= (ntBITS (8, 11) << 12); // Rd
1626 case 0xD3: // ROR{S}<c>.W <Rd>,<Rn>,<Rm>
1632 * ainstr |= (ntBITS (8, 11) << 12); // Rd
1641 ARMword Rd = ntBITS (8, 11);
1648 // REV<c>.W <Rd>,<Rm>
1653 state->Reg [Rd] =
1665 // UADD8<c> <Rd>,<Rn>,<Rm>
1668 // UADD16<c> <Rd>,<Rn>,<Rm>
1672 * ainstr |= (Rd << 12);
1682 ARMword Rd = ntBITS (8, 11);
1690 // CLZ<c> <Rd>,<Rm>
1696 // SEL<c> <Rd>,<Rn>,<Rm>
1701 * ainstr |= (Rd << 12);
1711 ARMword Rd = ntBITS (8, 11);
1716 // SMLA<x><y><c> <Rd>,<Rn>,<Rm>,<Ra>
1737 state->Reg[Rd] = res;
1743 // MLS<c> <Rd>,<Rn>,<Rm>,<Ra>
1744 state->Reg[Rd] = state->Reg[Ra] - (state->Reg[Rn] * state->Reg[Rm]);
1751 // MUL<c> <Rd>,<Rn>,<Rm>
1752 state->Reg[Rd] = state->Reg[Rn] * state->Reg[Rm];
1754 // MLA<c> <Rd>,<Rn>,<Rm>,<Ra>
1755 state->Reg[Rd] = state->Reg[Rn] * state->Reg[Rm] + state->Reg[Ra];
1858 ARMword Rd = (tBIT (7) << 3) | tBITS (0, 2);
1860 state->Reg[Rd] += state->Reg[Rm];
1864 case 0x4600: // MOV<c> <Rd>,<Rm>
1867 // instr [7] = Rd<high>
1869 // instr [2,0] = Rd<low>
1870 ARMword Rd = (tBIT(7) << 3) | tBITS (0, 2);
1871 // FIXME: Check for Rd == 15 and ITblock.
1872 state->Reg[Rd] = state->Reg[tBITS (3, 6)];
2039 | ((tinstr & 0x0007) << 12); /* Rd */
2046 0xE0900000, /* ADDS Rd,Rs,Rn */
2047 0xE0500000, /* SUBS Rd,Rs,Rn */
2048 0xE2900000, /* ADDS Rd,Rs,#imm3 */
2049 0xE2500000 /* SUBS Rd,Rs,#imm3 */
2056 | ((tinstr & 0x0007) << (12 - 0)); /* Rd */
2063 * ainstr = 0xE3A00000; /* MOV Rd,#imm8 */
2071 * ainstr = 0xE3500000; /* CMP Rd,#imm8 */
2079 ? 0xE2400000 /* SUB Rd,Rd,#imm8 */
2080 : 0xE2800000; /* ADD Rd,Rd,#imm8 */
2105 { 0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */
2106 { 0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */
2107 { 0xE1B00010, t_shift}, /* MOVS Rd,Rd,LSL Rs */
2108 { 0xE1B00030, t_shift}, /* MOVS Rd,Rd,LSR Rs */
2109 { 0xE1B00050, t_shift}, /* MOVS Rd,Rd,ASR Rs */
2110 { 0xE0B00000, t_norm}, /* ADCS Rd,Rd,Rs */
2111 { 0xE0D00000, t_norm}, /* SBCS Rd,Rd,Rs */
2112 { 0xE1B00070, t_shift}, /* MOVS Rd,Rd,ROR Rs */
2113 { 0xE1100000, t_norm}, /* TST Rd,Rs */
2114 { 0xE2700000, t_neg}, /* RSBS Rd,Rs,#0 */
2115 { 0xE1500000, t_norm}, /* CMP Rd,Rs */
2116 { 0xE1700000, t_norm}, /* CMN Rd,Rs */
2117 { 0xE1900000, t_norm}, /* ORRS Rd,Rd,Rs */
2118 { 0xE0100090, t_mul} , /* MULS Rd,Rd,Rs */
2119 { 0xE1D00000, t_norm}, /* BICS Rd,Rd,Rs */
2120 { 0xE1F00000, t_norm} /* MVNS Rd,Rs */
2135 { 0xE0000000, t_norm}, /* AND Rd,Rd,Rs */
2136 { 0xE0200000, t_norm}, /* EOR Rd,Rd,Rs */
2137 { 0xE1A00010, t_shift}, /* MOV Rd,Rd,LSL Rs */
2138 { 0xE1A00030, t_shift}, /* MOV Rd,Rd,LSR Rs */
2139 { 0xE1A00050, t_shift}, /* MOV Rd,Rd,ASR Rs */
2140 { 0xE0A00000, t_norm}, /* ADC Rd,Rd,Rs */
2141 { 0xE0C00000, t_norm}, /* SBC Rd,Rd,Rs */
2142 { 0xE1A00070, t_shift}, /* MOV Rd,Rd,ROR Rs */
2143 { 0xE1100000, t_norm}, /* TST Rd,Rs */
2144 { 0xE2600000, t_neg}, /* RSB Rd,Rs,#0 */
2145 { 0xE1500000, t_norm}, /* CMP Rd,Rs */
2146 { 0xE1700000, t_norm}, /* CMN Rd,Rs */
2147 { 0xE1800000, t_norm}, /* ORR Rd,Rd,Rs */
2148 { 0xE0000090, t_mul} , /* MUL Rd,Rd,Rs */
2149 { 0xE1C00000, t_norm}, /* BIC Rd,Rd,Rs */
2150 { 0xE1E00000, t_norm} /* MVN Rd,Rs */
2159 | ((tinstr & 0x0007) << 12) /* Rd */
2163 *ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
2168 *ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
2172 *ainstr |= ((tinstr & 0x0007) << 16) /* Rd */
2181 ARMword Rd = ((tinstr & 0x0007) >> 0);
2184 Rd += 8;
2189 case 0x1: /* ADD Rd,Rd,Hs */
2193 | (Rd << 16) /* Rn */
2194 | (Rd << 12) /* Rd */
2197 case 0x5: /* CMP Rd,Hs */
2201 | (Rd << 16) /* Rn */
2202 | (Rd << 12) /* Rd */
2205 case 0x9: /* MOV Rd,Hs */
2209 | (Rd << 12) /* Rd */
2215 | ((tinstr & 0x0078) >> 3); /* Rd */
2223 | ((tinstr & 0x0078) >> 3); /* Rd */
2236 case 9: /* LDR Rd,[PC,#imm8] */
2239 | ((tinstr & 0x0700) << (12 - 8)) /* Rd */
2251 0xE7800000, /* STR Rd,[Rb,Ro] */
2252 0xE7C00000, /* STRB Rd,[Rb,Ro] */
2253 0xE7900000, /* LDR Rd,[Rb,Ro] */
2254 0xE7D00000 /* LDRB Rd,[Rb,Ro] */
2257 | ((tinstr & 0x0007) << (12 - 0)) /* Rd */
2265 0xE18000B0, /* STRH Rd,[Rb,Ro] */
2266 0xE19000D0, /* LDRSB Rd,[Rb,Ro] */
2267 0xE19000B0, /* LDRH Rd,[Rb,Ro] */
2268 0xE19000F0 /* LDRSH Rd,[Rb,Ro] */
2271 | ((tinstr & 0x0007) << (12 - 0)) /* Rd */
2276 case 12: /* STR Rd,[Rb,#imm5] */
2277 case 13: /* LDR Rd,[Rb,#imm5] */
2278 case 14: /* STRB Rd,[Rb,#imm5] */
2279 case 15: /* LDRB Rd,[Rb,#imm5] */
2283 0xE5800000, /* STR Rd,[Rb,#imm5] */
2284 0xE5900000, /* LDR Rd,[Rb,#imm5] */
2285 0xE5C00000, /* STRB Rd,[Rb,#imm5] */
2286 0xE5D00000 /* LDRB Rd,[Rb,#imm5] */
2291 | ((tinstr & 0x0007) << (12 - 0)) /* Rd */
2296 case 16: /* STRH Rd,[Rb,#imm5] */
2297 case 17: /* LDRH Rd,[Rb,#imm5] */
2302 | ((tinstr & 0x0007) << (12 - 0)) /* Rd */
2307 case 18: /* STR Rd,[SP,#imm8] */
2308 case 19: /* LDR Rd,[SP,#imm8] */
2313 | ((tinstr & 0x0700) << (12 - 8)) /* Rd */
2316 case 20: /* ADD Rd,PC,#imm8 */
2317 case 21: /* ADD Rd,SP,#imm8 */
2325 | ((tinstr & 0x0700) << (12 - 8)) /* Rd */
2333 | ((tinstr & 0x0700) << (12 - 8)) /* Rd */