sim/arm/armemu.c

94   switch (BITS (5, 6))					\
124   switch (BITS (5, 6))					\
153   switch (BITS (5, 6))						\
180   switch (BITS (5, 6))						\
210   switch (BITS (5, 6))						\
237   switch (BITS (5, 6))						\
273   switch (BITS (20, 27))
307 	Rd = BITS (12, 15);
308 	val = (BITS (16, 19) << 12) | BITS (0, 11);
321 	Rd = BITS (12, 15);
322 	val = (BITS (16, 19) << 12) | BITS (0, 11);
335 	Rd = BITS (12, 15);
336 	Rn = BITS (16, 19);
337 	Rm = BITS (0, 3);
345 	switch (BITS (4, 11))
535 	if (BITS (8, 11) != 0xF)
538 	Rn = BITS (16, 19);
539 	Rd = BITS (12, 15);
540 	Rm = BITS (0, 3);
552 	switch (BITS (4, 7))
689 	Rn = BITS (16, 19);
690 	Rd = BITS (12, 15);
691 	Rm = BITS (0, 3);
711 	switch (BITS (4, 11))
729 	    if (BITS (4, 6) == 0x7)
737 	Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF);
741 	if (BITS (16, 19) == 0xf)
743 	  state->Reg[BITS (12, 15)] = Rm;
746 	  state->Reg[BITS (12, 15)] += Rm;
754 	switch (BITS (4, 11))
770 	      if (BITS (16, 19) != 0xF)
773 	      Rd = BITS (12, 15);
774 	      Rm = BITS (0, 3);
793 	      if (BITS (16, 19) != 0xF)
796 	      Rd = BITS (12, 15);
797 	      Rm = BITS (0, 3);
819 	Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF);
823 	if (BITS (16, 19) == 0xf)
825 	  state->Reg[BITS (12, 15)] = Rm;
828 	  state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm;
836 	switch (BITS (4, 11))
854 	    if (BITS (4, 6) == 0x7)
862 	Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF);
864 	if (BITS (16, 19) == 0xf)
866 	  state->Reg[BITS (12, 15)] = Rm;
869 	  state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm;
878 	switch (BITS (4, 11))
886 	    if (BITS (16, 19) != 0xF)
888 	    Rd = BITS (12, 15);
890 	    Rm = state->Reg[BITS (0, 3)];
907 	Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF);
909 	if (BITS (16, 19) == 0xf)
911 	  state->Reg[BITS (12, 15)] = Rm;
914 	  state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm;
936 	if (BITS (4, 6) != 0x1)
939 	Rd = BITS (12, 15);
946 	lsb = BITS (7, 11);
947 	msb = BITS (16, 20);
958 	Rn = BITS (0, 3);
974 	if (BITS (4, 6) != 0x5)
977 	Rd = BITS (12, 15);
984 	Rn = BITS (0, 3);
991 	lsb = BITS (7, 11);
992 	widthm1 = BITS (16, 20);
1017 	if (BITS (4, 6) != 0x5)
1020 	Rd = BITS (12, 15);
1027 	Rn = BITS (0, 3);
1034 	lsb = BITS (7, 11);
1035 	widthm1 = BITS (16, 20);
1059   switch (BITS (20, 27))
1063       switch (BITS (4, 11))
1069 	    int sreg = (BITS (0, 3) << 1) | BIT (5);
1073 		state->Reg[BITS (12, 15)] = VFP_uword (sreg);
1074 		state->Reg[BITS (16, 19)] = VFP_uword (sreg + 1);
1078 		VFP_uword (sreg)     = state->Reg[BITS (12, 15)];
1079 		VFP_uword (sreg + 1) = state->Reg[BITS (16, 19)];
1088 	    int dreg = BITS (0, 3) | (BIT (5) << 4);
1094 			   BITS (12, 15), BITS (16, 19), dreg);
1096 		state->Reg[BITS (12, 15)] = VFP_dword (dreg);
1097 		state->Reg[BITS (16, 19)] = VFP_dword (dreg) >> 32;
1101 		VFP_dword (dreg) = state->Reg[BITS (16, 19)];
1103 		VFP_dword (dreg) |= state->Reg[BITS (12, 15)];
1107 			   dreg, BITS (16, 19), BITS (12, 15),
1114 	  fprintf (stderr, "SIM: VFP: Unimplemented move insn %x\n", BITS (20, 27));
1122       if (BITS (0, 6) != 0x10 || BITS (8, 11) != 0xA)
1123 	fprintf (stderr, "SIM: VFP: Unimplemented move insn %x\n", BITS (20, 27));
1126 	  int sreg = (BITS (16, 19) << 1) | BIT (7);
1136       fprintf (stderr, "SIM: VFP: Unimplemented move insn %x\n", BITS (20, 27));
1371 	      if (BITS (25, 27) == 5) /* BLX(1) */
1538 	      if (BIT (20) == 0 && BITS (25, 27) == 0)
1540 		  if (BITS (4, 7) == 0xD)
1556 			  state->Reg[BITS (12, 15)] =
1558 			  state->Reg[BITS (12, 15) + 1] =
1566 		  else if (BITS (4, 7) == 0xF)
1581 					    state->Reg[BITS (12, 15)]);
1583 					    state->Reg[BITS (12, 15) + 1]);
1597 	  switch ((int) BITS (20, 27))
1603 	      if (BITS (4, 11) == 0xB)
1609 	      if (BITS (4, 7) == 0xD)
1614 	      if (BITS (4, 7) == 0xF)
1620 	      if (BITS (4, 7) == 9)
1652 	      if ((BITS (4, 11) & 0xF9) == 0x9)
1657 	      if (BITS (4, 7) == 9)
1696 	      if (BITS (4, 11) == 0xB)
1703 	      if (BITS (4, 7) == 9)
1734 	      if ((BITS (4, 11) & 0xF9) == 0x9)
1739 	      if (BITS (4, 7) == 9)
1779 	      if (BITS (4, 7) == 0xB)
1785 	      if (BITS (4, 7) == 0xD)
1790 	      if (BITS (4, 7) == 0xF)
1803 	      if ((BITS (4, 7) & 0x9) == 0x9)
1827 	      if (BITS (4, 7) == 0xB)
1841 	      if ((BITS (4, 7) & 0x9) == 0x9)
1865 	      if (BITS (4, 11) == 0xB)
1871 	      if (BITS (4, 7) == 0xD)
1876 	      if (BITS (4, 7) == 0xF)
1883 	      if (BITS (4, 7) == 0x9)
1900 	      if ((BITS (4, 11) & 0xF9) == 0x9)
1906 	      if (BITS (4, 7) == 0x9)
1938 	      if (BITS (4, 11) == 0xB)
1944 	      if (BITS (4, 7) == 0x9)
1961 	      if ((BITS (4, 11) & 0xF9) == 0x9)
1965 	      if (BITS (4, 7) == 0x9)
1997 	      if (BITS (4, 7) == 0xB)
2003 	      if (BITS (4, 7) == 0xD)
2008 	      if (BITS (4, 7) == 0xF)
2013 	      if (BITS (4, 7) == 0x9)
2030 	      if ((BITS (4, 7) & 0x9) == 0x9)
2034 	      if (BITS (4, 7) == 0x9)
2062 	      if (BITS (4, 7) == 0xB)
2069 	      if (BITS (4, 7) == 0x9)
2086 	      if ((BITS (4, 7) & 0x9) == 0x9)
2091 	      if (BITS (4, 7) == 0x9)
2124 		      ARMword op1 = state->Reg[BITS (0, 3)];
2125 		      ARMword op2 = state->Reg[BITS (8, 11)];
2126 		      ARMword Rn = state->Reg[BITS (12, 15)];
2142 		      state->Reg[BITS (16, 19)] = op1 + Rn;
2146 		  if (BITS (4, 11) == 5)
2149 		      ARMword op1 = state->Reg[BITS (0, 3)];
2150 		      ARMword op2 = state->Reg[BITS (16, 19)];
2157 		      state->Reg[BITS (12, 15)] = result;
2162 	      if (BITS (4, 11) == 0xB)
2168 	      if (BITS (4, 7) == 0xD)
2173 	      if (BITS (4, 7) == 0xF)
2179 	      if (BITS (4, 11) == 9)
2202 	      else if ((BITS (0, 11) == 0) && (LHSReg == 15))
2220 	      if ((BITS (4, 11) & 0xF9) == 0x9)
2249 		  if (BITS (4, 7) == 3)
2268 		      && (BIT (5) == 0 || BITS (12, 15) == 0))
2271 		      ARMdword op1 = state->Reg[BITS (0, 3)];
2272 		      ARMdword op2 = state->Reg[BITS (8, 11)];
2286 			  ARMword Rn = state->Reg[BITS (12, 15)];
2292 		      state->Reg[BITS (16, 19)] = result;
2296 		  if (BITS (4, 11) == 5)
2299 		      ARMword op1 = state->Reg[BITS (0, 3)];
2300 		      ARMword op2 = state->Reg[BITS (16, 19)];
2309 		      state->Reg[BITS (12, 15)] = result;
2314 	      if (BITS (4, 11) == 0xB)
2320 	      if (BITS (4, 27) == 0x12FFF1)
2326 	      if (BITS (4, 7) == 0xD)
2331 	      if (BITS (4, 7) == 0xF)
2339 		  if (BITS (4, 7) == 0x7)
2392 	      if ((BITS (4, 11) & 0xF9) == 0x9)
2424 		      ARMdword op1 = state->Reg[BITS (0, 3)];
2425 		      ARMdword op2 = state->Reg[BITS (8, 11)];
2439 		      dest = (ARMdword) state->Reg[BITS (16, 19)] << 32;
2440 		      dest |= state->Reg[BITS (12, 15)];
2442 		      state->Reg[BITS (12, 15)] = dest;
2443 		      state->Reg[BITS (16, 19)] = dest >> 32;
2447 		  if (BITS (4, 11) == 5)
2450 		      ARMword op1 = state->Reg[BITS (0, 3)];
2451 		      ARMword op2 = state->Reg[BITS (16, 19)];
2468 		      state->Reg[BITS (12, 15)] = result;
2473 	      if (BITS (4, 7) == 0xB)
2479 	      if (BITS (4, 7) == 0xD)
2484 	      if (BITS (4, 7) == 0xF)
2490 	      if (BITS (4, 11) == 9)
2509 	      else if ((BITS (0, 11) == 0) && (LHSReg == 15))
2527 	      if ((BITS (4, 7) & 0x9) == 0x9)
2567 		  if (BIT (4) == 0 && BIT (7) == 1 && BITS (12, 15) == 0)
2570 		      ARMword op1 = state->Reg[BITS (0, 3)];
2571 		      ARMword op2 = state->Reg[BITS (8, 11)];
2584 		      state->Reg[BITS (16, 19)] = op1 * op2;
2588 		  if (BITS (4, 11) == 5)
2591 		      ARMword op1 = state->Reg[BITS (0, 3)];
2592 		      ARMword op2 = state->Reg[BITS (16, 19)];
2609 		      state->Reg[BITS (12, 15)] = result;
2616 		  if (BITS (4, 11) == 0xF1 && BITS (16, 19) == 0xF)
2619 		      ARMword op1 = state->Reg[BITS (0, 3)];
2626 		      state->Reg[BITS (12, 15)] = result;
2631 	      if (BITS (4, 7) == 0xB)
2637 	      if (BITS (4, 7) == 0xD)
2642 	      if (BITS (4, 7) == 0xF)
2667 	      if ((BITS (4, 7) & 0x9) == 0x9)
2709 	      if (BITS (4, 11) == 0xB)
2715 	      if (BITS (4, 7) == 0xD)
2720 	      if (BITS (4, 7) == 0xF)
2733 	      if ((BITS (4, 11) & 0xF9) == 0x9)
2745 	      if (BITS (4, 11) == 0xB)
2751 	      if (BITS (4, 7) == 0xD)
2756 	      if (BITS (4, 7) == 0xF)
2768 	      if ((BITS (4, 11) & 0xF9) == 0x9)
2779 	      if (BITS (4, 7) == 0xB)
2785 	      if (BITS (4, 7) == 0xD)
2790 	      else if (BITS (4, 7) == 0xF)
2803 	      if ((BITS (4, 7) & 0x9) == 0x9)
2815 	      if (BITS (4, 7) == 0xB)
2821 	      if (BITS (4, 7) == 0xD)
2826 	      if (BITS (4, 7) == 0xF)
2838 	      if ((BITS (4, 7) & 0x9) == 0x9)
3021 	      dest = BITS (0, 11);
3022 	      dest |= (BITS (16, 19) << 12);
3087 	      dest  = BITS (0, 11);
3088 	      dest |= (BITS (16, 19) << 12);
4051 		  if (BITS (0, 19) == 0xfdefe)
4298 		  else if (BITS (12, 15) == 15 || BITS (16, 19) == 15)
4307 		      if (BITS (4, 7) != 0x00)
4313 		      else if (BITS (0, 3) != 0x00)
4318 			  state->Accumulator = state->Reg[BITS (12, 15)];
4319 			  state->Accumulator += (ARMdword) state->Reg[BITS (16, 19)] << 32;
4348 		      if (BITS (4, 7) != 0x00)
4354 		      else if (BITS (0, 3) != 0x00)
4364 			  state->Reg[BITS (12, 15)] = state->Accumulator;
4365 			  state->Reg[BITS (16, 19)] = t1;
4476 		switch (BITS (18, 19))
4479 		    if (BITS (4, 11) == 1 && BITS (16, 17) == 0)
4496 		    if (BITS (4, 11) == 1 && BITS (16, 17) == 0)
4528 		    if (BITS (4, 11) == 1)
4607 		      switch (BITS (20, 27))
4610 			  if (BITS (16, 19) == 0x1
4611 			      && BITS (0, 11) == 0xA10)
4641 			  if (BITS (0,6) != 0x10 || BITS (8,11) != 0xA)
4644 			    state->Reg[BITS (12, 15)] = VFP_uword (BITS (16, 19) << 1 | BIT (7));
4646 			    VFP_uword (BITS (16, 19) << 1 | BIT (7)) = state->Reg[BITS (12, 15)];
4700 	      if (!ARMul_OSHandleSWI (state, BITS (0, 23)))
4750       shamt = state->Reg[BITS (8, 11)] & 0xff;
4751       switch ((int) BITS (5, 6))
4791       shamt = BITS (7, 11);
4792       switch ((int) BITS (5, 6))
4841       shamt = state->Reg[BITS (8, 11)] & 0xff;
4842       switch ((int) BITS (5, 6))
4918       shamt = BITS (7, 11);
4920       switch ((int) BITS (5, 6))
5089   shamt = BITS (7, 11);
5090   switch ((int) BITS (5, 6))
5133   return BITS (0, 3) | (BITS (8, 11) << 4);
5271   offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->Reg[RHSReg];
5384   offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->Reg[RHSReg];
5923   nRdHi = BITS (16, 19);
5924   nRdLo = BITS (12, 15);
5925   nRs = BITS (8, 11);
5926   nRm = BITS (0, 3);
6034   nRdHi = BITS (16, 19);
6035   nRdLo = BITS (12, 15);