sim/arm/armemu.c

271   ARMword Rn;
336 	Rn = BITS (16, 19);
339 	if (Rd == 15 || Rn == 15 || Rm == 15)
342 	val1 = state->Reg[Rn];
347 	  case 0xF1: /* QADD16<c> <Rd>,<Rn>,<Rm>.  */
371 	  case 0xF3: /* QASX<c> <Rd>,<Rn>,<Rm>.  */
407 	  case 0xF5: /* QSAX<c> <Rd>,<Rn>,<Rm>.  */
443 	  case 0xF7: /* QSUB16<c> <Rd>,<Rn>,<Rm>.  */
467 	  case 0xF9: /* QADD8<c> <Rd>,<Rn>,<Rm>.  */
491 	  case 0xFF: /* QSUB8<c> <Rd>,<Rn>,<Rm>.  */
527 	/* U{ADD|SUB}{8|16}<c> <Rd>, <Rn>, <Rm>
530 	   instr[19,16] = Rn
538 	Rn = BITS (16, 19);
542 	if (Rn == 15 || Rd == 15 || Rm == 15)
549 	valn = state->Reg[Rn];
654 	/* PKHBT<c> <Rd>,<Rn>,<Rm>{,LSL #<imm>}
655 	   PKHTB<c> <Rd>,<Rn>,<Rm>{,ASR #<imm>}
656 	   SXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>}
658 	   SEL<c> <Rd>,<Rn>,<Rm>
662 	   instr[19,16] = Rn
689 	Rn = BITS (16, 19);
692 	if (Rn == 15 || Rm == 15 || Rd == 15)
699 	res  = (state->Reg[(state->Cpsr & GE0) ? Rn : Rm]) & 0xFF;
700 	res |= (state->Reg[(state->Cpsr & GE1) ? Rn : Rm]) & 0xFF00;
701 	res |= (state->Reg[(state->Cpsr & GE2) ? Rn : Rm]) & 0xFF0000;
702 	res |= (state->Reg[(state->Cpsr & GE3) ? Rn : Rm]) & 0xFF000000;
926 	   BFI<c> <Rd>,<Rn>,#<lsb>,#<width>
934 	   instr[ 3, 0] = Rn (BFI) / 1111 (BFC).  */
958 	Rn = BITS (0, 3);
959 	if (Rn != 0xF)
961 	    ARMword val = state->Reg[Rn] & ~(-(1 << ((msb + 1) - lsb)));
968     case 0x7a: /* SBFX<c> <Rd>,<Rn>,#<lsb>,#<width>.  */
984 	Rn = BITS (0, 3);
985 	if (Rn == 15)
994 	sval = state->Reg[Rn];
1008 	/* UBFX<c> <Rd>,<Rn>,#<lsb>,#<width>
1015 	   instr[ 3, 0] = Rn.  */
1027 	Rn = BITS (0, 3);
1028 	if (Rn == 15)
1037 	val = state->Reg[Rn];
2126 		      ARMword Rn = state->Reg[BITS (12, 15)];
2140 		      if (AddOverflow (op1, Rn, op1 + Rn))
2142 		      state->Reg[BITS (16, 19)] = op1 + Rn;
2286 			  ARMword Rn = state->Reg[BITS (12, 15)];
2288 			  if (AddOverflow (result, Rn, result + Rn))
2290 			  result += Rn;