dist/opcodes/s390-opc.c

47 #define R_8         1             /* GPR starting at position 8 */
302 #define INSTR_RIE_RRP      6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxhg */
303 #define INSTR_RIE_RRPU     6, { R_8,R_12,U4_32,J16_16,0,0 }      /* e.g. crj   */
304 #define INSTR_RIE_RRP0     6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. cgrjne */
305 #define INSTR_RIE_RRI0     6, { R_8,R_12,I16_16,0,0,0 }          /* e.g. ahik  */
306 #define INSTR_RIE_RUPI     6, { R_8,I8_32,U4_12,J16_16,0,0 }     /* e.g. cij   */
307 #define INSTR_RIE_R0PI     6, { R_8,I8_32,J16_16,0,0,0 }         /* e.g. cijne */
308 #define INSTR_RIE_RUPU     6, { R_8,U8_32,U4_12,J16_16,0,0 }     /* e.g. clij  */
309 #define INSTR_RIE_R0PU     6, { R_8,U8_32,J16_16,0,0,0 }         /* e.g. clijne */
310 #define INSTR_RIE_R0IU     6, { R_8,I16_16,U4_32,0,0,0 }         /* e.g. cit   */
311 #define INSTR_RIE_R0I0     6, { R_8,I16_16,0,0,0,0 }             /* e.g. citne */
312 #define INSTR_RIE_R0UU     6, { R_8,U16_16,U4_32,0,0,0 }         /* e.g. clfit */
313 #define INSTR_RIE_R0U0     6, { R_8,U16_16,0,0,0,0 }             /* e.g. clfitne */
314 #define INSTR_RIE_RUI0     6, { R_8,I16_16,U4_12,0,0,0 }         /* e.g. lochi */
315 #define INSTR_RIE_RRUUU    6, { R_8,R_12,U8_16,U8_24,U8_32,0 }   /* e.g. rnsbg */
317 #define INSTR_RIL_RP       6, { R_8,J32_16,0,0,0,0 }             /* e.g. brasl */
319 #define INSTR_RIL_RI       6, { R_8,I32_16,0,0,0,0 }             /* e.g. afi   */
320 #define INSTR_RIL_RU       6, { R_8,U32_16,0,0,0,0 }             /* e.g. alfi  */
322 #define INSTR_RI_RI        4, { R_8,I16_16,0,0,0,0 }             /* e.g. ahi   */
323 #define INSTR_RI_RP        4, { R_8,J16_16,0,0,0,0 }             /* e.g. brct  */
324 #define INSTR_RI_RU        4, { R_8,U16_16,0,0,0,0 }             /* e.g. tml   */
326 #define INSTR_RIS_RURDI    6, { R_8,I8_32,U4_12,D_20,B_16,0 }    /* e.g. cib   */
327 #define INSTR_RIS_R0RDI    6, { R_8,I8_32,D_20,B_16,0,0 }        /* e.g. cibne */
328 #define INSTR_RIS_RURDU    6, { R_8,U8_32,U4_12,D_20,B_16,0 }    /* e.g. clib  */
329 #define INSTR_RIS_R0RDU    6, { R_8,U8_32,D_20,B_16,0,0 }        /* e.g. clibne*/
389 #define INSTR_RR_R0        2, { R_8, 0,0,0,0,0 }                 /* e.g. spm   */
390 #define INSTR_RR_RR        2, { R_8,R_12,0,0,0,0 }               /* e.g. lr    */
396 #define INSTR_RRS_RRRDU    6, { R_8,R_12,U4_32,D_20,B_16 }       /* e.g. crb   */
397 #define INSTR_RRS_RRRD0    6, { R_8,R_12,D_20,B_16,0 }           /* e.g. crbne */
398 #define INSTR_RSE_RRRD     6, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. lmh   */
401 #define INSTR_RSE_RURD     6, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icmh  */
405 #define INSTR_RSI_RRP      4, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxh  */
406 #define INSTR_RSY_RRRD     6, { R_8,R_12,D20_20,B_16,0,0 }       /* e.g. stmy  */
408 #define INSTR_RSY_RURD     6, { R_8,U4_12,D20_20,B_16,0,0 }      /* e.g. icmh  */
409 #define INSTR_RSY_RURD2    6, { R_8,D20_20,B_16,U4_12,0,0 }      /* e.g. loc   */
410 #define INSTR_RSY_R0RD     6, { R_8,D20_20,B_16,0,0,0 }          /* e.g. locne */
415 #define INSTR_RS_R0RD      4, { R_8,D_20,B_16,0,0,0 }            /* e.g. sll   */
417 #define INSTR_RS_RRRD      4, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. cs    */
419 #define INSTR_RS_RURD      4, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icm   */
422 #define INSTR_RXE_RRRD     6, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. lg    */
423 #define INSTR_RXE_RRRDU    6, { R_8,D_20,X_12,B_16,U4_32,0 }     /* e.g. lcbb  */
428 #define INSTR_RXF_RRRDR    6, { R_32,R_8,D_20,X_12,B_16,0 }      /* e.g. .insn */
429 #define INSTR_RXY_RRRD     6, { R_8,D20_20,X_12,B_16,0,0 }       /* e.g. ly    */
437 #define INSTR_RX_RRRD      4, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. l     */
452 #define INSTR_SS_RRRDRD    6, { D_20,R_8,B_16,D_36,B_32,R_12 }   /* e.g. mvck  */
453 #define INSTR_SS_RRRDRD2   6, { R_8,D_20,B_16,R_12,D_36,B_32 }   /* e.g. plo   */
454 #define INSTR_SS_RRRDRD3   6, { R_8,R_12,D_20,B_16,D_36,B_32 }   /* e.g. lmd   */
455 #define INSTR_SSF_RRDRD    6, { D_20,B_16,D_36,B_32,R_8,0 }      /* e.g. mvcos */
479 #define INSTR_VRS_RVRDU    6, { R_8,V_12,D_20,B_16,U4_32,0 }     /* e.g. vlgv  */
480 #define INSTR_VRS_RVRD     6, { R_8,V_12,D_20,B_16,0,0 }         /* e.g. vlgvb */
516 #define INSTR_VRR_RV0U     6, { R_8,V_12,U4_24,0,0,0 }           /* e.g. vcvb  */
517 #define INSTR_VRR_RV0UU    6, { R_8,V_12,U4_24,U4_28,0,0 }       /* e.g. vcvb  */