Lines Matching defs:X_MASK
3270 #define P_X_MASK (PREFIX_MASK | X_MASK)
3750 #define X_MASK XRC (0x3f, 0x3ff, 1)
3753 #define XBF_MASK (X_MASK | (3 << 21))
3814 /* An X_MASK with the RA/VA field fixed. */
3815 #define XRA_MASK (X_MASK | RA_MASK)
3822 /* An X_MASK with the RB field fixed. */
3823 #define XRB_MASK (X_MASK | RB_MASK)
3825 /* An X_MASK with the RT field fixed. */
3826 #define XRT_MASK (X_MASK | RT_MASK)
3834 /* An X_MASK with the RA and RB fields fixed. */
3835 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
3846 /* An X_MASK with the RT and RA fields fixed. */
3847 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
3849 /* An X_MASK with the RT and RB fields fixed. */
3850 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
3855 /* An X_MASK with the RT, RA and RB fields fixed. */
3856 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
3904 #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22))
3914 #define XTO_MASK (X_MASK | TO_MASK)
3920 #define XTLB_MASK (X_MASK | SH_MASK)
3945 /* An X_MASK, but with the EH bit clear. */
3946 #define XEH_MASK (X_MASK & ~((uint64_t )1))
4031 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
4044 #define XSPR_MASK (X_MASK | SPR_MASK)
4248 {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
4319 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
4320 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
4408 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
4410 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
4460 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
4462 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
4476 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
4477 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
4759 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
4761 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
4799 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
4800 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5796 {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
6201 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
6202 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
6204 {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
6205 {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
6230 {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
6235 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
6242 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
6244 {"icbt", X(31,22), X_MASK, POWER5|BOOKE|PPCE300, 0, {CT, RA0, RB}},
6246 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
6247 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
6249 {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6250 {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6251 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6252 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6259 {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6260 {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
6262 {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
6263 {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
6265 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
6266 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
6268 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
6276 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
6283 {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
6284 {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
6289 {"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}},
6291 {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
6293 {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
6301 {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
6313 {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
6317 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
6321 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
6322 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
6327 {"cntlzdm", X(31,59), X_MASK, POWER10, 0, {RA, RS, RB}},
6329 {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
6330 {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
6353 {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
6363 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
6364 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
6379 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
6381 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
6385 {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
6397 {"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}},
6409 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
6413 {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RSB}},
6414 {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
6415 {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RSB}},
6416 {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
6424 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
6426 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
6444 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
6454 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
6455 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
6457 {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
6459 {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
6461 {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
6462 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
6464 {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
6465 {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
6467 {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
6468 {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
6473 {"pdepd", X(31,156), X_MASK, POWER10, 0, {RA, RS, RB}},
6475 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
6477 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
6481 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
6483 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
6491 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
6502 {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
6504 {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
6506 {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}},
6507 {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
6509 {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
6510 {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
6512 {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
6513 {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
6518 {"pextd", X(31,188), X_MASK, POWER10, 0, {RA, RS, RB}},
6522 {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
6524 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
6546 {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
6548 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
6550 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
6552 {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
6554 {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
6555 {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
6557 {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
6558 {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
6561 {"cfuged", X(31,220), X_MASK, POWER10, 0, {RA, RS, RB}},
6563 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
6567 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
6569 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
6592 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
6602 {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
6603 {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
6604 {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
6606 {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
6608 {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
6609 {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
6611 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
6613 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
6615 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
6616 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
6618 {"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}},
6622 {"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}},
6628 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
6635 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
6642 {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, 0, {RB, RSO, RIC, PRS, X_R}},
6645 {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
6649 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
6650 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
6653 {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
6654 {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
6655 {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
6657 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
6661 {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
6662 {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
6664 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
6666 {"mfdcrux", X(31,291), X_MASK, PPC464|PPC476, 0, {RS, RA}},
6668 {"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}},
6669 {"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}},
6673 {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
6675 {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
6682 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
6684 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
6688 {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
6689 {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
6691 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
6727 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
6728 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
6730 {"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}},
6732 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
6741 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
6742 {"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}},
6811 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
7041 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
7043 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
7047 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
7049 {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7062 {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
7065 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
7069 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
7075 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
7076 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
7078 {"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}},
7080 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7091 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
7097 {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
7099 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
7100 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
7102 {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
7104 {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
7105 {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
7107 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7111 {"mtdcrux", X(31,419), X_MASK, PPC464|PPC476, 0, {RA, RS}},
7113 {"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}},
7115 {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
7130 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
7132 {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
7151 {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RSB}},
7152 {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
7153 {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RSB}},
7154 {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
7192 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
7193 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
7195 {"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}},
7208 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
7209 {"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}},
7470 {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
7474 {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
7475 {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
7481 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}},
7483 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7485 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7496 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
7505 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
7509 {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
7510 {"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
7512 {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
7514 {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
7533 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
7535 {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
7536 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
7538 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
7539 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
7541 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
7543 {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
7544 {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
7545 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
7546 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
7548 {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
7549 {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
7554 {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
7555 {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
7557 {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
7558 {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
7560 {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
7561 {"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
7563 {"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}},
7565 {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
7567 {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
7577 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
7582 {"cnttzdm", X(31,571), X_MASK, POWER10, 0, {RA, RS, RB}},
7586 {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
7587 {"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
7589 {"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}},
7591 {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
7599 {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
7600 {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
7618 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
7621 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
7623 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
7625 {"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}},
7627 {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
7637 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
7641 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
7643 {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
7644 {"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
7646 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
7665 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
7667 {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
7668 {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
7670 {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
7671 {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
7673 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
7675 {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
7676 {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
7678 {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
7679 {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
7681 {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
7682 {"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
7684 {"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}},
7686 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
7692 {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
7694 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
7696 {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
7697 {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
7699 {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
7700 {"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
7702 {"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}},
7704 {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
7722 {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
7723 {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
7725 {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
7727 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
7729 {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
7730 {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
7732 {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
7733 {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
7736 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
7738 {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
7740 {"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}},
7742 {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
7773 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
7775 {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
7776 {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
7778 {"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}},
7782 {"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}},
7783 {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
7794 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
7795 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
7800 {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
7804 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
7806 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
7808 {"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
7809 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
7811 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
7812 {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
7813 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
7814 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
7816 {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
7817 {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
7820 {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
7822 {"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}},
7823 {"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}},
7824 {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
7829 {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
7831 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
7833 {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
7835 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
7839 {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
7841 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
7842 {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
7843 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
7844 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
7849 {"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}},
7859 {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
7869 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
7872 {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
7876 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
7878 {"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}},
7888 {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
7892 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
7896 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
7904 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
7917 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
7918 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
7923 {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
7925 {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
7927 {"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
7928 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
7930 {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
7931 {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
7933 {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
7934 {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
7942 {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
7944 {"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}},
7948 {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
7950 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
7964 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
7966 {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
7968 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
7969 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
7971 {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
7973 {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
7974 {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
7979 {"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}},
7996 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
8000 {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
8004 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
8011 {"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}},
8030 {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
8116 {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8117 {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8162 {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8163 {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8186 {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
8191 {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
8209 {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8210 {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8212 {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8213 {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8215 {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
8216 {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
8222 {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8223 {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8235 {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8236 {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8238 {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8239 {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8245 {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
8247 {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
8248 {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
8254 {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8255 {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8257 {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
8258 {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
8260 {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
8261 {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
8268 {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8269 {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8504 {"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
8505 {"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
8510 {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8511 {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8516 {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
8517 {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
8590 {"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
8591 {"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
8596 {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8597 {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8615 {"xscmpeqqp", X(63,68), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
8629 {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8633 {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
8652 {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
8658 {"xscmpgeqp", X(63,196), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
8665 {"xscmpgtqp", X(63,228), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
8667 {"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
8668 {"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
8673 {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
8674 {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
8676 {"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
8677 {"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
8679 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
8680 {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
8682 {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8683 {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8688 {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8689 {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8694 {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8695 {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8700 {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8701 {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8706 {"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
8707 {"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
8709 {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8710 {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8712 {"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
8713 {"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
8715 {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8716 {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8728 {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
8732 {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
8733 {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
8735 {"xsmaxcqp", X(63,676), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
8737 {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
8744 {"xsmincqp", X(63,740), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
8746 {"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
8747 {"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
8749 {"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
8750 {"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
8770 {"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
8771 {"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
8787 {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
8794 {"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
8795 {"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
8797 {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
8805 {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
9756 {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
9758 {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},