Lines Matching defs:FSL
3090 /* Xilinx FSL related masks and macros */
3091 #define FSL FCRT + 1
3096 #define URT FSL + 1
4549 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
4572 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
4584 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
4586 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
4626 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
4649 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
4689 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
4728 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},