dist/opcodes/mt-desc.c

196   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
337   { "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
341   { "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16,
345   { "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1,
349   { "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3,
353   { "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
357   { "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2,
361   { "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3,
365   { "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
369   { "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
373   { "rownum2", MT_OPERAND_ROWNUM2, HW_H_UINT, 9, 3,
377   { "rc1", MT_OPERAND_RC1, HW_H_UINT, 11, 1,
381   { "rc2", MT_OPERAND_RC2, HW_H_UINT, 6, 1,
385   { "cbrb", MT_OPERAND_CBRB, HW_H_UINT, 10, 1,
389   { "cell", MT_OPERAND_CELL, HW_H_UINT, 9, 3,
393   { "dup", MT_OPERAND_DUP, HW_H_UINT, 6, 1,
397   { "ctxdisp", MT_OPERAND_CTXDISP, HW_H_UINT, 5, 6,
401   { "fbdisp", MT_OPERAND_FBDISP, HW_H_UINT, 15, 6,
405   { "type", MT_OPERAND_TYPE, HW_H_UINT, 21, 2,
409   { "mask", MT_OPERAND_MASK, HW_H_UINT, 25, 16,
413   { "bankaddr", MT_OPERAND_BANKADDR, HW_H_UINT, 25, 13,
417   { "incamt", MT_OPERAND_INCAMT, HW_H_UINT, 19, 8,
421   { "xmode", MT_OPERAND_XMODE, HW_H_UINT, 23, 1,
425   { "mask1", MT_OPERAND_MASK1, HW_H_UINT, 22, 3,
429   { "ball", MT_OPERAND_BALL, HW_H_UINT, 19, 1,
433   { "brc", MT_OPERAND_BRC, HW_H_UINT, 18, 3,
437   { "rda", MT_OPERAND_RDA, HW_H_UINT, 25, 1,
441   { "wr", MT_OPERAND_WR, HW_H_UINT, 24, 1,
445   { "ball2", MT_OPERAND_BALL2, HW_H_UINT, 15, 1,
449   { "brc2", MT_OPERAND_BRC2, HW_H_UINT, 14, 3,
453   { "perm", MT_OPERAND_PERM, HW_H_UINT, 25, 2,
457   { "a23", MT_OPERAND_A23, HW_H_UINT, 23, 1,
461   { "cr", MT_OPERAND_CR, HW_H_UINT, 22, 3,
465   { "cbs", MT_OPERAND_CBS, HW_H_UINT, 19, 2,
469   { "incr", MT_OPERAND_INCR, HW_H_UINT, 17, 6,
473   { "length", MT_OPERAND_LENGTH, HW_H_UINT, 15, 3,
477   { "cbx", MT_OPERAND_CBX, HW_H_UINT, 14, 3,
481   { "ccb", MT_OPERAND_CCB, HW_H_UINT, 11, 1,
485   { "cdb", MT_OPERAND_CDB, HW_H_UINT, 10, 1,
489   { "mode", MT_OPERAND_MODE, HW_H_UINT, 25, 2,
493   { "id", MT_OPERAND_ID, HW_H_UINT, 14, 1,
497   { "size", MT_OPERAND_SIZE, HW_H_UINT, 13, 14,
501   { "fbincr", MT_OPERAND_FBINCR, HW_H_UINT, 23, 4,
505   { "loopsize", MT_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
509   { "imm16l", MT_OPERAND_IMM16L, HW_H_UINT, 23, 16,
513   { "rc3", MT_OPERAND_RC3, HW_H_UINT, 7, 1,
517   { "cb1sel", MT_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
521   { "cb2sel", MT_OPERAND_CB2SEL, HW_H_UINT, 22, 3,