gdb/nat/aarch64-linux-hw-point.c

45 /* Return starting byte 0..7 incl. of a watchpoint encoded by CTRL.  */
60 /* Utility function that returns the length in bytes of a watchpoint
79     error (_("Unexpected hardware watchpoint length register value 0x%x"),
85 /* Given the hardware breakpoint or watchpoint type TYPE and its
87    breakpoint/watchpoint control register.  */
113       perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
126 /* Addresses to be written to the hardware breakpoint and watchpoint
132    watchpoint to be accepted by the kernel (via ptrace call), its
134    Despite these limitations, the unaligned watchpoint is supported in
172 /* Given the (potentially unaligned) watchpoint address in ADDR and
176    valid values to write to the hardware watchpoint value and control
179    The given watchpoint may get truncated if more than one hardware
182    of the remaining part of the watchpoint (which can be processed
186    Essentially, unaligned watchpoint is achieved by minimally
188    if necessary, splitting the watchpoint over several hardware
189    watchpoint registers.
192    in the hardware watchpoint control register, the offset from the
199    from a watchpoint trap if there is no change to the watched region.
202    the watchpoint fault address discovered by
207    higher-level watchpoint management is only aware of original
208    watched regions, and will think that some unknown watchpoint has
232   /* The address put into the hardware watchpoint value register must
245       /* Need more than one watchpoint register; truncate at the
256 	 accommodate this watchpoint.  */
282    information about the change of one hardware breakpoint/watchpoint
340 /* Notify each thread that their IDXth breakpoint/watchpoint register
388 	/* No update needed for this watchpoint?  */
414 /* Record the insertion of one breakpoint/watchpoint, as represented
494 /* Record the removal of one breakpoint/watchpoint, as represented by
583    from that it is an aligned watchpoint to be handled.  */
596 /* Insert/remove unaligned watchpoint by calling
599    to be written to one or more hardware watchpoint registers.
665 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
670 			      int tid, int watchpoint)
680   count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
681   addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
682   ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
695 	      watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
699       if (watchpoint && errno == EINVAL
704 	  aarch64_linux_set_debug_regs (state, tid, watchpoint);
715 					bool watchpoint)
717   int count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
721   const CORE_ADDR *addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
722   const unsigned int *ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
731 /* Print the values of the cached breakpoint/watchpoint registers.  */
744 		  type == hw_write ? "hw-write-watchpoint"
745 		  : (type == hw_read ? "hw-read-watchpoint"
746 		     : (type == hw_access ? "hw-access-watchpoint"
777   /* Get hardware watchpoint register info.  */
786 	  warning (_("Unexpected number of hardware watchpoint registers"
834   /* Must have hardware watchpoint debug register(s).  */
838   /* We support unaligned watchpoint address and arbitrary length,
840      doesn't exceed size of the total area that all watchpoint debug
853   /* All tests passed so we are likely to be able to set the watchpoint.
855      we don't check the current usage of the watchpoint registers, and
856      there may not be enough registers available for this watchpoint.