config/ia64/ia64.cc

1406 /* Split a post-reload TImode or TFmode reference into two DImode
1429       out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1430       out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1442 	   quantity into a pair of DImode constants.  */
1475 		  (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1477 		  (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1485 		  (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1486 		out[1] = adjust_address (in, DImode, 0);
1494 	    out[0] = adjust_automodify_address (in, DImode, 0, 0);
1495 	    out[1] = adjust_automodify_address (in, DImode, 0, 8);
1504 	      (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1506 	      (in, DImode,
1524 	      (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1530 		out[1] = adjust_automodify_address (in, DImode, 0, 8);
1542 		    out[1] = adjust_automodify_address (in, DImode, base, 8);
1551 		      (in, DImode, gen_rtx_POST_MODIFY
1684      DImode loads for convenience.  We also need to support XFmode stores
1716 	  emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1719 	  emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1732       out[0] = gen_rtx_REG (DImode, REGNO (op0));
1733       out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1735       emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1736       emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1764 	  in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
1765 	  in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1767 	  emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1768 	  emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1865       ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode,
1867 				     GEN_INT (magic), DImode);
2179   addr = convert_memory_address (DImode, addr);
2180   b0 = gen_rtx_REG (DImode, R_BR (0));
2211 	     gen_rtx_REG (DImode, GR_REG (25)));
2248       tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp));
2278       tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
2374   if ((mode == SImode || mode == DImode)
2431   old_reg = gen_reg_rtx (DImode);
2432   cmp_reg = gen_reg_rtx (DImode);
2435   if (mode != DImode)
2437       val = simplify_gen_subreg (DImode, val, mode, 0);
2438       emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
2445   ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
2455       new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX,
2457       new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true);
2460     new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
2463   if (mode != DImode)
2507   emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label);
3089       spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
3113 	    = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
3114 				   gen_rtx_PLUS (DImode,
3125 	      rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
3159 	      rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
3321   emit_insn (gen_rtx_SET (gen_rtx_ZERO_EXTRACT (DImode, r3, GEN_INT (12),
3616       ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
3628 				     gen_rtx_REG (DImode, AR_PFS_REGNUM)));
3658 	  offset = gen_rtx_REG (DImode, regno);
3670 				     gen_rtx_PLUS (DImode,
3688 	    = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3694 	  ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3698       reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3721       reg = gen_rtx_REG (DImode, regno);
3733       reg = gen_rtx_REG (DImode, PR_REG (0));
3736 	  alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3740 	  /* ??? Denote pr spill/fill by a DImode move that modifies all
3753 	  alt_reg = gen_rtx_REG (DImode, alt_regno);
3764       reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3775       reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3782       reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3785 	  alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3799 	  alt_reg = gen_rtx_REG (DImode, alt_regno);
3809       reg = gen_rtx_REG (DImode, BR_REG (0));
3812           alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3826 	  alt_reg = gen_rtx_REG (DImode, alt_regno);
3836       insn = emit_move_insn (gen_rtx_REG (DImode,
3849 	reg = gen_rtx_REG (DImode, regno);
3859 	alt_reg = gen_rtx_REG (DImode, alt_regno);
3860 	reg = gen_rtx_REG (DImode, regno);
3941 	  alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3947 	  alt_reg = gen_rtx_REG (DImode, alt_regno);
3951       reg = gen_rtx_REG (DImode, PR_REG (0));
3964 	    = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3970 	  ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3982       alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]);
3983       reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3989       alt_reg = gen_rtx_REG (DImode, alt_regno);
3992       reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
4000 	  alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
4006 	  alt_reg = gen_rtx_REG (DImode, alt_regno);
4010       reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
4019          alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
4025 	  alt_reg = gen_rtx_REG (DImode, alt_regno);
4029       reg = gen_rtx_REG (DImode, BR_REG (0));
4046 	reg = gen_rtx_REG (DImode, regno);
4056 	alt_reg = gen_rtx_REG (DImode, alt_regno);
4059 	reg = gen_rtx_REG (DImode, regno);
4076       reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
4113 	  offset = gen_rtx_REG (DImode, regno);
4123 				 gen_rtx_PLUS (DImode,
4132     emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
4157 	  insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
4217 	  src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
4257     src = gen_rtx_REG (DImode, BR_REG (0));
4295   if (regno == PR_REG (0) && mode == DImode)
4327     return mode == DImode;
4330     return mode == DImode;
4777       emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)),
4843       /* Fill in the GR regs.  We must use DImode here, not the hfa mode.  */
4847 	  machine_mode gr_mode = DImode;
4893 					  gen_rtx_REG (DImode,
4917 		     gen_rtx_REG (DImode, basereg + cum->words + offset),
4928 	(BYTES_BIG_ENDIAN && arg.mode == SFmode) ? DImode : arg.mode;
5292 					  gen_rtx_REG (DImode,
5361    e    Print 64 - constant, for DImode rotates.
5590       x = simplify_subreg (DImode, x, GET_MODE (x), 0);
5976       /* This can happen when we take a BImode subreg of a DImode value,
5977 	 and that DImode value winds up in some non-GR register.  */
8106      ZERO_EXTEND will always be DImode.  */
10624       if (! target || ! register_operand (target, DImode))
10625 	target = gen_reg_rtx (DImode);
10751   set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
10754   set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
10757   set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
10761   set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad");
10781   set_optab_libfunc (sdiv_optab, DImode, "__milli_divI");
10782   set_optab_libfunc (udiv_optab, DImode, "__milli_divU");
10783   set_optab_libfunc (smod_optab, DImode, "__milli_remI");
10784   set_optab_libfunc (umod_optab, DImode, "__milli_remU");
10809   set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10811   set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10813   set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10815   set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10853   return (mode == SImode || mode == DImode);
11489   tmp = gen_reg_rtx (DImode);
11490   hi = gen_lowpart (DImode, hi);
11491   lo = gen_lowpart (DImode, lo);
11580       temp = gen_reg_rtx (DImode);
11581       emit_insn (gen_extzv (temp, gen_lowpart (DImode, d->op0),
11933    In BR regs, we can't change the DImode at all.
11935    but we can change e.g. DImode to SImode, and V2SFmode into DImode.  */