config/sparc/sparc.c

1013 	   && REGNO (recog_data.operand[1]) == reg)
1016 	      && REGNO (recog_data.operand[2]) == reg));
1234 	  const unsigned int dest_reg = REGNO (SET_DEST (single_set (insn)));
1256 		  && REGNO (SET_DEST (set)) > 31)
1260 		  if (REGNO (SET_DEST (set)) == dest_reg)
1367 	       && REGNO (SET_DEST (set)) > 31
1368 	       && REGNO (SET_DEST (set)) % 2 != 0)
1371 	  const unsigned int x = REGNO (SET_DEST (set)) - 1;
1391 	      dest = REGNO (recog_data.operand[0]);
1392 	      src1 = REGNO (recog_data.operand[1]);
1393 	      src2 = REGNO (recog_data.operand[2]);
1416 	      dest = REGNO (recog_data.operand[0]);
1417 	      src1 = REGNO (recog_data.operand[1]);
1438 	       && REGNO (SET_DEST (set)) < 32)
1461 		  && REGNO (dest) < 32
1470 			       && REGNO (src) < 32
1471 			       && REGNO (src) != REGNO (x)))
1488 	       && REGNO (SET_DEST (set)) > 31)
1493 	  const unsigned int x = REGNO (SET_DEST (set));
1509 		&& REGNO (SET_DEST (set)) == y))
1553 		      && (REGNO (dest) == x
1554 			  || (REGNO (dest) == y && size == 8)))
1561 		      if (REGNO (src) == y || (REGNO (src) == x && size == 8))
1565 		      if (REGNO (src) == x && size == 4)
2371       && (SPARC_FP_REG_P (REGNO (operands[0]))
2383       if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
2388       if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
2511       temp = gen_rtx_REG (DImode, REGNO (temp));
2593 	      temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
2664 		  temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
3042 		  || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
3687   int regno = REGNO (reg);
4066       && SPARC_FP_REG_P (REGNO (src_reg)))
4168 	  regno = REGNO (SET_DEST (expr));
4181   regno = REGNO (SET_DEST (pat));
4232       || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
4233       || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat))))
4316     insn = gen_load_pcrel_symdi (op0, op1, op2, GEN_INT (REGNO (op0)));
4318     insn = gen_load_pcrel_symsi (op0, op1, op2, GEN_INT (REGNO (op0)));
4383 		     reg_names[REGNO (got_register_rtx)] + 1);
4386 					 REGNO (got_register_rtx));
4532       && ORIGINAL_REGNO (x) == REGNO (pic_offset_table_rtx))
4673       if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
4674 	  || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
4679       if ((! SPARC_INT_REG_P (REGNO (rs1))
4680 	   && REGNO (rs1) != FRAME_POINTER_REGNUM
4681 	   && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
4683 	      && (! SPARC_INT_REG_P (REGNO (rs2))
4684 		  && REGNO (rs2) != FRAME_POINTER_REGNUM
4685 		  && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
5275       int regno = REGNO (base);
5517 /* Return whether REGNO, a global or FP register, must be saved/restored.  */
5545 /* Return whether REGNO, a local or in register, must be saved/restored.  */
5563   if (got_register_rtx && regno == REGNO (got_register_rtx))
7388    REGNO is the hard register the union will be passed in.  */
7425    REGNO is the hard register the vector will be passed in.  */
8415 	    v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
8419 		gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
8967       if (REGNO (*where) >= 8 && REGNO (*where) < 24)      /* oX or lX */
8969       if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
8974 				   OUTGOING_REGNO (REGNO (*where)));
8980 				  OUTGOING_REGNO (REGNO (*where)));
9003 	  && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
9012 	  && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
9081   if ((REGNO (reg) % 2) == 0 && mem_min_alignment (mem, 8))
9136   const int regno1 = REGNO (reg1);
9142   const int regno2 = REGNO (reg2);
9181 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
9193   if (REGNO (reg1) % 2 != 0)
9197   if (TARGET_V9 && SPARC_INT_REG_P (REGNO (reg1)))
9200   return (REGNO (reg1) == REGNO (reg2) - 1);
9260           reg1 = REGNO (XEXP (addr1, 0));
9271       reg1 = REGNO (addr1);
9284   if (reg1 != REGNO (XEXP (addr2, 0)))
9287   if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
9325   if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
9326     return (REGNO (reg) % 2 == 0);
9442       else if (REGNO (x) < 8)
9443 	fputs (reg_names[REGNO (x)], file);
9444       else if (REGNO (x) >= 24 && REGNO (x) < 32)
9445 	fputs (reg_names[REGNO (x)-16], file);
9452 	fputs (reg_names[REGNO (x)+1], file);
9454 	fputs (reg_names[REGNO (x)], file);
9459 	fputs (reg_names[REGNO (x)], file);
9461 	fputs (reg_names[REGNO (x)+1], file);
9466       fputs (reg_names[REGNO (x)+1], file);
9471       fputs (reg_names[REGNO (x)+2], file);
9476       fputs (reg_names[REGNO (x)+3], file);
9480       if (REGNO (x) == SPARC_ICC_REG)
9503 	fputs (reg_names[REGNO (x)], file);
9715     fputs (reg_names[REGNO (x)], file);
9757     fputs (reg_names[REGNO (addr)], file);
9778 	  fputs (reg_names[REGNO (base)], file);
9782 	    fprintf (file, "+%s", reg_names[REGNO (index)]);
10618     y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
10621       && df && DF_REG_DEF_COUNT (REGNO (y)) == 1)