config/rs6000/rs6000.c

1887      modes and DImode.  */
2226     DImode,
2987     rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS;	/* DImode  */
3139 	      reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3146       reg_addr[DImode].scalar_in_vmx_p = true;
3291 		 "DImode multipliciation cost     = %d\n"
3293 		 "DImode division cost            = %d\n"
3590       rs6000_pmode = DImode;
5810 	     except when TARGET_POWERPC64 and mode is DImode or
5811 	     wider, so the register mode must be DImode.  */
5812 	  && rs6000_is_valid_and_mask (GEN_INT (low), DImode))
5842 					     DImode);
5876 	    mode = DImode;
5891 	    insns = num_insns_constant_multi (val, DImode);
5894 	    insns += num_insns_constant_multi (val, DImode);
6541 	      rtx tmp = gen_reg_rtx (DImode);
6633       rtx di_tmp = gen_reg_rtx (DImode);
6859       if (GET_MODE (elt) != DImode)
6861 	  rtx tmp = gen_reg_rtx (DImode);
6866 	elt = force_reg (DImode, elt);
7227 				  gen_rtx_AND (DImode,
7228 					       gen_rtx_ASHIFT (DImode,
7257 	  rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7275 	    rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7289 	    rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7291 	    rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
8770     tlsreg = gen_rtx_REG (DImode, 13);
9029    auto-increment.  For DFmode, DDmode and DImode with a constant plus
9034    32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9114       && (TARGET_POWERPC64 || mode != DImode)
9427 				      DImode);
9429 				      DImode);
9450 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9475       temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9481 			gen_rtx_IOR (DImode, copy_rtx (temp),
9486       temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9493 			gen_rtx_IOR (DImode, copy_rtx (temp),
9496 		      gen_rtx_ZERO_EXTEND (DImode,
9502       temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9505       rtx one = gen_rtx_AND (DImode, temp, GEN_INT (0xffffffff));
9506       rtx two = gen_rtx_ASHIFT (DImode, temp, GEN_INT (32));
9507       emit_move_insn (dest, gen_rtx_IOR (DImode, one, two));
9512       temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9518 			gen_rtx_IOR (DImode, copy_rtx (temp),
9521 		      gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9525 			gen_rtx_IOR (DImode, copy_rtx (temp),
9530       temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9536 			gen_rtx_IOR (DImode, copy_rtx (temp),
9540 		      gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9544 			gen_rtx_IOR (DImode, copy_rtx (temp),
9548 			gen_rtx_IOR (DImode, copy_rtx (temp),
9610     RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
9612     RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
9844       && mode == DImode
9845       && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
9846 	  || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
10303       set_conv_libfunc (sfix_optab, DImode, mode, "__fixtfdi");
10304       set_conv_libfunc (ufix_optab, DImode, mode, "__fixunstfdi");
10306       set_conv_libfunc (sfloat_optab, mode, DImode, "__floatditf");
10307       set_conv_libfunc (ufloat_optab, mode, DImode, "__floatunditf");
10415       set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
10416       set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
10420       set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
10421       set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
10564   if (mode != DImode && mode != SImode)
10619   /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
10621   if (mode == DImode)
10642   if (mode == DImode && ne == 0)
10650   if (mode == DImode && nb == 63)
10707   /* DImode rotates need rld*.  */
10708   if (mode == DImode && code == ROTATE)
10754   if (mode == DImode && ne == 0)
10764   if (mode == DImode && nb == 63)
10772   if (mode == DImode
10833   /* DImode rotates need rldimi.  */
10834   if (mode == DImode && code == ROTATE)
10878       && (!dot || mode == DImode)
10942   /* If it is one stretch of ones, it is DImode; shift left, mask, then
10948       gcc_assert (mode == DImode);
10953 	  rtx tmp1 = gen_reg_rtx (DImode);
10954 	  rtx tmp2 = gen_reg_rtx (DImode);
10995   gcc_assert (mode == DImode);
10997   /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
11022       rtx tmp1 = gen_reg_rtx (DImode);
11023       rtx tmp2 = gen_reg_rtx (DImode);
11024       rtx tmp3 = gen_reg_rtx (DImode);
13139       /* Write second word of DImode or DFmode reference.  Works on register
14408       gen_float_kfdi2_hw,		/* KFmode <- DImode (signed).  */
14409       gen_floatuns_kfdi2_hw,		/* KFmode <- DImode (unsigned).  */
14414       gen_fix_kfdi2_hw,			/* DImode <- KFmode (signed).  */
14415       gen_fixuns_kfdi2_hw,		/* DImode <- KFmode (unsigned).  */
14424       gen_float_tfdi2_hw,		/* TFmode <- DImode (signed).  */
14425       gen_floatuns_tfdi2_hw,		/* TFmode <- DImode (unsigned).  */
14430       gen_fix_tfdi2_hw,			/* DImode <- TFmode (signed).  */
14431       gen_fixuns_tfdi2_hw,		/* DImode <- TFmode (unsigned).  */
14688   if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
14690       PUT_MODE (condition_rtx, DImode);
15424   if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
15786       rtx xor1_result = gen_reg_rtx (DImode);
15787       rtx xor2_result = gen_reg_rtx (DImode);
15788       rtx or_result = gen_reg_rtx (DImode);
15789       rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
15790       rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
15791       rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
15792       rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
16399   return TARGET_32BIT ? SImode : DImode;
21281       else if (mode == DImode)
21318 	  if (GET_MODE (XEXP (x, 1)) == DImode)
21408       if (TARGET_EXTSWSLI && mode == DImode
21425 	  if (mode == DImode)
22167       tmp2 = expand_mult (DImode, tmp1,
22171       tmp2 = force_reg (DImode, tmp2);
22234 	  tmp1 = gen_reg_rtx (DImode);
22237 	  tmp2 = gen_reg_rtx (DImode);
22239 	  tmp3 = gen_reg_rtx (DImode);
22242 	  tmp4 = gen_reg_rtx (DImode);
22244 	  tmp5 = gen_reg_rtx (DImode);
22247 	  tmp6 = gen_reg_rtx (DImode);
22904     mode = TARGET_32BIT ? SImode : DImode;
22936   if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
25468       && GET_CODE (scratch) == SCRATCH && GET_MODE (scratch) == DImode)
25578   if (mem_mode == SImode && reg_mode == DImode
25863       && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
25926 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system.  These
25964 	  op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
26053   /* If this is DImode, use the specialized version that can run before
26055   if (mode == DImode && !TARGET_POWERPC64)
26065   sub_mode = (TARGET_POWERPC64) ? DImode : SImode;