Lines Matching +defs:label +defs:offset
362 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
366 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
405 is more limited than normal d-form addressing in that the offset must be
2271 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2704 instructions are enabled. The offset for 128-bit VSX registers is
2705 only 12-bits. While GPRs can handle the full offset range, VSX
2717 /* Vector pairs can do both indexed and offset loads if the
2718 instructions are enabled, otherwise they can only do offset loads
2720 only do offset loads. */
4421 long offset = strtol (str, &endp, 0);
4424 "-mstack-protector-guard-offset=");
4426 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4427 || (TARGET_64BIT && (offset & 3)))
4428 error ("%qs is not a valid offset in %qs", str,
4429 "-mstack-protector-guard-offset=");
4431 rs6000_stack_protector_guard_offset = offset;
4802 rs6000_loop_align (rtx label)
4811 bb = BLOCK_FOR_INSN (label);
6911 /* Add offset to field within buffer matching vector element. */
6931 /* Return the offset within a memory object (MEM) of a vector type to a given
6935 Otherwise, we use a base register temporary to calculate the offset after
6957 /* Shift the element to get the byte offset from the element number. */
6972 a constant offset (ELEMENT_OFFSET). If the address is not valid, we can
6992 HOST_WIDE_INT offset
6995 if (offset == 0)
7000 rtx plus = gen_rtx_PLUS (Pmode, op0, GEN_INT (offset));
7059 /* A simple indirect address can be converted into a reg + offset
7064 /* For references to local static variables, fold a constant offset into the
7069 /* Optimize D-FORM addresses with constant offset with a constant element, to
7070 include the element offset in the address directly. */
7079 /* op0 should never be r0, because r0+offset is not valid. But it
7084 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
7085 rtx offset_rtx = GEN_INT (offset);
7091 add the two elements in the current address. Then add the offset.
7093 Previously, we tried to add the offset to OP1 and change the
7096 had a constant element offset (due to the way ADDI is defined).
7098 offset, it has the benefit that if D-FORM instructions are
7099 allowed, the offset is part of the memory access to the vector
7115 The address offset overflowed the 16 or 34 bit offset size;
7541 /* Is this a valid prefixed address? If the bottom four bits of the offset
7544 forcing the unaligned offset to a GPR. */
7595 /* Given an address, return a constant offset term if one exists. */
7619 /* This tests that a lo_sum {constant, symbol, symbol+offset} is valid for
7623 reg + offset. */
7643 unsigned HOST_WIDE_INT offset = 0;
7652 offset = INTVAL (XEXP (x, 1));
7657 offset = INTVAL (x);
7659 offset = 0; // We assume code labels are Pmode aligned
7699 else if ((offset & 3) || (align & 3))
7712 else if ((offset & 3) || (align & 3))
7721 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7722 return SIGNED_16BIT_OFFSET_EXTRA_P (offset, extra);
7727 powerpc64 this means the offset must be divisible by 4.
7730 Accept direct, indexed, offset, lo_sum and tocref. Since this is
7736 "offsetting" here we mean a further offset to access parts of the
7737 MEM. It's fine to have a lo_sum where the inner address is offset
7738 from a sym, since the same sym+offset will appear in the high part
7744 unsigned HOST_WIDE_INT offset;
7756 offset are non-zero, we could use a prefixed instruction (which does not
7758 of forcing the unaligned offset to a GPR. */
7776 offset = INTVAL (op);
7777 if (TARGET_POWERPC64 && (offset & 3) != 0)
7785 /* For lo_sum addresses, we must allow any offset except one that
7787 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7789 return SIGNED_16BIT_OFFSET_EXTRA_P (offset, extra);
7793 enforce an offset divisible by 4 even for 32-bit. */
7798 unsigned HOST_WIDE_INT offset;
7803 offset are non-zero, we could use a prefixed instruction (which does not
7805 of forcing the unaligned offset to a GPR. */
7816 offset = INTVAL (op);
7817 if ((offset & 3) != 0)
7825 /* For lo_sum addresses, we must allow any offset except one that
7827 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7829 return SIGNED_16BIT_OFFSET_EXTRA_P (offset, extra);
7860 /* The vector pair/quad types support offset addressing if the
7861 underlying vectors support offset addressing. */
7912 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
7934 replacing memory addresses with an anchor plus offset. We
7936 VEC for the given offset but that seems like too much work. */
7945 offset += SYMBOL_REF_BLOCK_OFFSET (op);
7987 lsb = offset & -offset;
7997 rtx base, offset;
7999 split_const (op, &base, &offset);
8054 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
8128 unsigned HOST_WIDE_INT offset;
8146 offset = INTVAL (XEXP (x, 1));
8162 else if (offset & 3)
8177 else if (offset & 3)
8186 return SIGNED_34BIT_OFFSET_EXTRA_P (offset, extra);
8188 return SIGNED_16BIT_OFFSET_EXTRA_P (offset, extra);
8545 rtx x, y, offset;
8560 offset = NULL_RTX;
8565 offset = XEXP (y, 1);
8583 if (offset != NULL_RTX)
8584 y = gen_rtx_PLUS (Pmode, y, offset);
8949 /* IE, or 64-bit offset LE. */
9031 with offset word aligned.
9066 /* Handle prefixed addresses (PC-relative or 34-bit offset). */
9099 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9175 this assuming that the adjustable offset must be valid for the
9184 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9186 are no offset restrictions in that case. Note that this
10552 not zero, store there the bit offset (counted from the right) where
10554 offset where it ends. */
11078 /* Extract an offset (if used) from the first addr. */
11087 /* The offset must be constant! */
11111 /* The offset must be constant. */
11130 /* The offset for the second addr must be 8 more than the first addr. */
11358 type = "offset";
11395 type = "vector d-form offset";
11399 /* Make sure the register class can handle offset addresses. */
11405 type = "offset #2";
11695 For VSX and Altivec, we may need a register to convert sp+offset into
11699 convert an offset address to indirect. */
11798 unsigned HOST_WIDE_INT offset = INTVAL (off);
11802 will be reloaded), and the offset is not a multiple of
11807 ? (1 /* legitimate_address_p allows any offset for lo_sum */
11808 && ((offset & 3) != 0
11809 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
11810 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
11811 && (offset & 3) != 0))
11842 unsigned HOST_WIDE_INT offset = INTVAL (off);
11849 have any offset so test for wrap in the low 16 bits.
11861 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
11862 : offset - (0x8000 - extra) < UNITS_PER_WORD)
12100 /* Make sure the register class can handle offset addresses. */
12137 /* Make sure the register class can handle offset addresses. */
12180 /* Convert reloads involving 64-bit gprs and misaligned offset
12320 can use D-form (register+offset) addressing. */
12939 /* Write out a function code label. */
13147 we have already done it, we can just use an offset of word. */
13576 HOST_WIDE_INT offset;
13583 offset = INTVAL (XEXP (x, 1));
13587 offset = 0;
13591 if (offset)
13592 fprintf (file, "%+" PRId64, offset);
13783 /* The magic 32768 offset here corresponds to the offset of
14250 label. */
14712 the operand template of the label, or NULL if the branch is really a
14724 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
14731 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
14805 if (label == NULL)
14816 if (label != NULL)
14821 s += sprintf (s, ",$+8\n\tb %s", label);
14823 s += sprintf (s, ",%s", label);
15499 emit_unlikely_jump (rtx cond, rtx label)
15501 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
15843 rtx label, x, mask, shift;
15868 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
15869 emit_label (XEXP (label, 0));
15881 emit_unlikely_jump (x, label);
15902 rtx label, x, cond, mask, shift;
15969 label = gen_label_rtx ();
15970 emit_label (label);
15971 label = gen_rtx_LABEL_REF (VOIDmode, label);
16004 emit_unlikely_jump (x, label);
16117 unsigned offset = 0;
16130 rtx dst2 = adjust_address (dst, reg_mode, offset);
16132 offset += size;
16141 unsigned offset = 0;
16149 rtx src2 = adjust_address (src, reg_mode, offset);
16150 offset += size;
16612 HOST_WIDE_INT offset = 0;
16638 Set this label equal to that label. */
16851 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16880 if (offset < 0)
16881 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16882 else if (offset)
16883 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16901 if (offset < 0)
16902 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16903 else if (offset > 0)
16904 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
17180 /* Now, we need to get the address of the label. */
17727 /* Try to determine base/offset/size parts of the given MEM.
17735 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
17748 *offset = 0;
17752 *offset += INTVAL (XEXP (addr_rtx, 1));
17782 locations overlap by at least 1 byte based on base reg/offset/size. */
20039 /* GET_PREV_LABEL gets the label name from the previous definition of
20062 static unsigned label = 0;
20082 label++;
20084 sprintf (local_label_0, "L%u$spb", label);
20132 rtx base, offset;
20152 offset =
20156 if (CONST_INT_P (offset))
20158 if (SMALL_INT (offset))
20159 return plus_constant (Pmode, base, INTVAL (offset));
20161 offset = force_reg (Pmode, offset);
20168 return gen_rtx_PLUS (Pmode, base, offset);
21052 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
21055 assemble_name (file, label);
21059 /* Output a symbol offset relative to the dbase for the current object.
21067 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
21070 assemble_name (file, label);
23004 /* Define the offset between two registers, FROM to be eliminated and its
23010 HOST_WIDE_INT offset;
23013 offset = info->push_p ? 0 : -info->total_size;
23016 offset = info->push_p ? 0 : -info->total_size;
23018 offset += info->fixed_size + info->vars_size + info->parm_size;
23021 offset = FRAME_GROWS_DOWNWARD
23025 offset = info->total_size;
23027 offset = info->push_p ? info->total_size : 0;
23029 offset = 0;
23033 return offset;
23056 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
23058 emit_move_insn (adjust_address (mem, mode, offset), value);
23415 size_t global_offset; /* offset of the option in global_options. */
23416 size_t target_offset; /* offset of the option in target options. */
25259 /* If the non prefixed instruction format doesn't support offset addressing,
25309 /* Everything below must be an offset address of some form. */
25328 HOST_WIDE_INT offset = INTVAL (op1);
25329 if (!SIGNED_INTEGER_34BIT_P (offset))
25353 if (!SIGNED_INTEGER_16BIT_P (offset))
25361 /* We have a 16-bit offset, see what default instruction format to use. */
25392 if ((offset & 3) == 0)
25403 if ((offset & 15) == 0)
25475 instruction format (D/DS/DQ) used for offset memory. */
25686 label optimization, this is recorded also. */
25745 /* Fills in the label name that should be used for a 476 link stack thunk. */
26082 int offset = i * sub_size;
26083 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
26084 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
26087 : simplify_subreg (sub_mode, op2, mode, offset));
26100 an addis instruction and a load with an offset that can be fused together on
26180 rtx new_addr, new_mem, orig_addr, offset;
26201 offset = XEXP (orig_addr, 1);
26202 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
26321 emit_fusion_load (rtx load_reg, rtx addis_reg, rtx offset, const char *insn_str)
26329 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
26332 fuse_ops[2] = offset;
26336 else if (GET_CODE (offset) == UNSPEC
26337 && XINT (offset, 1) == UNSPEC_TOCREL)
26348 fuse_ops[2] = XVECEXP (offset, 0, 0);
26352 else if (GET_CODE (offset) == PLUS
26353 && GET_CODE (XEXP (offset, 0)) == UNSPEC
26354 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
26355 && CONST_INT_P (XEXP (offset, 1)))
26357 rtx tocrel_unspec = XEXP (offset, 0);
26368 fuse_ops[3] = XEXP (offset, 1);
26372 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
26376 fuse_ops[2] = offset;
26381 fatal_insn ("Unable to generate load/store offset for fusion", offset);
26386 /* Given an address, convert it into the addis and load offset parts. Addresses