dist/opcodes/or1k-opinst.c

37 #define OUTPUT CGEN_OPINST_OUTPUT
48   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
54   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
62   { OUTPUT, "h_gpr_USI_9", HW_H_GPR, CGEN_MODE_USI, 0, 9, 0 },
63   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
70   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
78   { OUTPUT, "h_gpr_USI_9", HW_H_GPR, CGEN_MODE_USI, 0, 9, 0 },
79   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
88   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
108   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
114   { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
115   { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
116   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
123   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
138   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
146   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
154   { OUTPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
155   { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
156   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
164   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
172   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
180   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
188   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
197   { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
198   { OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
207   { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
208   { OUTPUT, "h_memory_UQI_addr", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 },
217   { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
218   { OUTPUT, "h_memory_UHI_addr", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 },
229   { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
230   { OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, COND_REF },
231   { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
238   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
245   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
252   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
262   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
263   { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
264   { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
275   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
276   { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
277   { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
287   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
288   { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
295   { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
296   { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
306   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
307   { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
316   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, COND_REF },
317   { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, COND_REF },
326   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, COND_REF },
327   { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, COND_REF },
333   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
340   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
350   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
351   { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
352   { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
363   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
364   { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
365   { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
375   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
376   { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
382   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
390   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, COND_REF },
397   { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
404   { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
416   { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
417   { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
418   { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
430   { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
431   { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
432   { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 },
444   { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 },
445   { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 },
446   { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 },
453   { OUTPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 },
460   { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
467   { OUTPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 },
474   { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
481   { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 },
488   { OUTPUT, "rDDI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RDDI), 0, 0 },
495   { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
502   { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 },
510   { OUTPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 },
518   { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
524 #undef OUTPUT