Lines Matching refs:LFETCHINCIMMED
2138 #define LFETCHINCIMMED(x6,hnt,h) M0, OpX6aHintHlf (7, x6, hnt, h), {MR3, IMM9b}, POSTINC, 0, NULL
2142 {"lfetch", LFETCHINCIMMED (0x2c, 0, 0)},
2144 {"lfetch.nt1", LFETCHINCIMMED (0x2c, 1, 0)},
2146 {"lfetch.nt2", LFETCHINCIMMED (0x2c, 2, 0)},
2148 {"lfetch.nta", LFETCHINCIMMED (0x2c, 3, 0)},
2150 {"lfetch.d4", LFETCHINCIMMED (0x2c, 0, 1)},
2151 {"lfetch.d5", LFETCHINCIMMED (0x2c, 1, 1)},
2152 {"lfetch.d6", LFETCHINCIMMED (0x2c, 2, 1)},
2153 {"lfetch.d7", LFETCHINCIMMED (0x2c, 3, 1)},
2154 {"lfetch.excl", LFETCHINCIMMED (0x2d, 0, 0)},
2156 {"lfetch.excl.nt1", LFETCHINCIMMED (0x2d, 1, 0)},
2158 {"lfetch.excl.nt2", LFETCHINCIMMED (0x2d, 2, 0)},
2160 {"lfetch.excl.nta", LFETCHINCIMMED (0x2d, 3, 0)},
2162 {"lfetch.excl.d4", LFETCHINCIMMED (0x2d, 0, 1)},
2163 {"lfetch.excl.d5", LFETCHINCIMMED (0x2d, 1, 1)},
2164 {"lfetch.excl.d6", LFETCHINCIMMED (0x2d, 2, 1)},
2165 {"lfetch.excl.d7", LFETCHINCIMMED (0x2d, 3, 1)},
2166 {"lfetch.fault", LFETCHINCIMMED (0x2e, 0, 0)},
2168 {"lfetch.fault.nt1", LFETCHINCIMMED (0x2e, 1, 0)},
2170 {"lfetch.fault.nt2", LFETCHINCIMMED (0x2e, 2, 0)},
2172 {"lfetch.fault.nta", LFETCHINCIMMED (0x2e, 3, 0)},
2174 {"lfetch.fault.d4", LFETCHINCIMMED (0x2e, 0, 1)},
2175 {"lfetch.fault.d5", LFETCHINCIMMED (0x2e, 1, 1)},
2176 {"lfetch.fault.d6", LFETCHINCIMMED (0x2e, 2, 1)},
2177 {"lfetch.fault.d7", LFETCHINCIMMED (0x2e, 3, 1)},
2178 {"lfetch.fault.excl", LFETCHINCIMMED (0x2f, 0, 0)},
2180 {"lfetch.fault.excl.nt1", LFETCHINCIMMED (0x2f, 1, 0)},
2182 {"lfetch.fault.excl.nt2", LFETCHINCIMMED (0x2f, 2, 0)},
2184 {"lfetch.fault.excl.nta", LFETCHINCIMMED (0x2f, 3, 0)},
2186 {"lfetch.fault.excl.d4", LFETCHINCIMMED (0x2f, 0, 1)},
2187 {"lfetch.fault.excl.d5", LFETCHINCIMMED (0x2f, 1, 1)},
2188 {"lfetch.fault.excl.d6", LFETCHINCIMMED (0x2f, 2, 1)},
2189 {"lfetch.fault.excl.d7", LFETCHINCIMMED (0x2f, 3, 1)},
2191 #undef LFETCHINCIMMED