include/opcode/metag.h

566   INSN_FPU,
854       (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
856       (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
858       (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
860       (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
862       (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
864       (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
866       (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
868       (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
870       (FCOND_UVS << field_shift), meta_mask, INSN_FPU, encoding, args }, \
872       (FCOND_FVC << field_shift), meta_mask, INSN_FPU, encoding, args }, \
874       (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
876       (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
878       (FCOND_FLE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
880       (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
882       (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
884       (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
886       (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
888       (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
890       (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
892       (FCOND_ULE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
894       (FCOND_NV << field_shift), meta_mask, INSN_FPU, encoding, args }
903       (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
905       (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
907       (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
909       (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
911       (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
913       (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
915       (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
917       (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
919       (FCOND_UVS << field_shift), meta_mask, INSN_FPU, encoding, args }, \
921       (FCOND_FVC << field_shift), meta_mask, INSN_FPU, encoding, args }, \
923       (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
925       (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
927       (FCOND_FLE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
929       (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
931       (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
933       (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
935       (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
937       (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
939       (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
941       (FCOND_ULE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
943       (FCOND_NV << field_shift), meta_mask, INSN_FPU, encoding, args },	\
1681 	       0xa1800201, 0xfff83e1f, INSN_FPU, ENC_MOV_PORT, 0),
1685       0xce000006, 0xfffc007f, INSN_FPU, ENC_MMOV, 0 },
1687       0xcf000006, 0xfffc007f, INSN_FPU, ENC_MMOV, 0 },
1691 		0xf0000080, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
1693       0xbe000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
1695       0xbf000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
1697       0xce000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
1699       0xcf000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
1701       0x08000144, 0xfe03e1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
1703       0x080001c4, 0xfe83c1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
1705       0x08000154, 0xfe03e1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
1707       0x080001d4, 0xfe83c1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
1709 		0xf0000000, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
1711       0xf0000001, 0xff800001, INSN_FPU, ENC_FMOV_I, 0 },
1713 		0xf0000100, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
1715       0xf0000180, 0xff8c21ff, INSN_FPU, ENC_FPACK, 0 },
1717       0xf00001c0, 0xff8c7fff, INSN_FPU, ENC_FSWAP, 0 },
1721 		0xf3000000, 0xfff4201f, INSN_FPU, ENC_FCMP, 0),
1723 		0xf3000081, 0xff84219f, INSN_FPU, ENC_FMINMAX, 0),
1725 		0xf3000001, 0xff84219f, INSN_FPU, ENC_FMINMAX, 0),
1729 		0xf2000121, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
1731 		0xf2000101, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
1733 		0xf2000320, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
1735 		0xf2000300, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
1737 		0xf2002120, 0xff842fff, INSN_FPU, ENC_FCONV, 0),
1739 		0xf2002100, 0xff842fbf, INSN_FPU, ENC_FCONV, 0),
1741 		0xf2002320, 0xff8c6fff, INSN_FPU, ENC_FCONV, 0),
1744 		0xf2000020, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
1746 		0xf2000000, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
1748 		0xf20000a0, 0xff8c40ff, INSN_FPU, ENC_FCONVX, 0),
1751 		0xf2000321, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
1753 		0xf2000301, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
1755 		0xf2002121, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
1757 		0xf2002101, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
1759 		0xf2002321, 0xff8c7fff, INSN_FPU, ENC_FCONV, 0),
1762 		0xf2000021, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
1764 		0xf2000001, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
1766 		0xf20000a1, 0xff8c40ff, INSN_FPU, ENC_FCONVX, 0),
1770 		0xf1000001, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
1772 		0xf1000100, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
1774 		0xf1000101, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
1778       0xf6000000, 0xfffc219f, INSN_FPU, ENC_FEARITH, 0 },
1780       0xf6000100, 0xfffc219f, INSN_FPU, ENC_FEARITH, 0 },
1783       0xf6000004, 0xff84211f, INSN_FPU, ENC_FEARITH, 0 },
1785       0xf6000104, 0xff84211f, INSN_FPU, ENC_FEARITH, 0 },
1788       0xf6000008, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
1790       0xf6000108, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
1792       0xf6000009, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
1794       0xf6000109, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
1797 		0xf5000000, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
1799 		0xf5000100, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
1801 		0xf5000001, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
1803 		0xf5000101, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
1806       0xf6000010, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
1808       0xf6000110, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
1810       0xf6000011, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
1812       0xf6000111, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
1815       0xf7000000, 0xff84391f, INSN_FPU, ENC_FREC, 0 },
1817       0xf7000100, 0xff84391f, INSN_FPU, ENC_FREC, 0 },
1821       0xf4000000, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
1823       0xf4000001, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
1825       0xf4000100, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
1829       0xce000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
1831       0xce000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
1833       0xcf000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
1836       0xbe000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
1838       0xbe000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
1840       0xbf000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
1844       0xcf000004, 0xffe03f9f, INSN_FPU, ENC_FGET_SET_ACF, 0 },
1846       0xbf000004, 0xffe03f9f, INSN_FPU, ENC_FGET_SET_ACF, 0 },