Lines Matching defs:X_MASK
3872 #define P_X_MASK (PREFIX_MASK | X_MASK)
4361 #define X_MASK XRC (0x3f, 0x3ff, 1)
4364 #define XBF_MASK (X_MASK | (3 << 21))
4409 /* An X_MASK with an accumulator register and the RA and RB fields fixed. */
4410 #define XACC_MASK (X_MASK | RA_MASK | RB_MASK | (3 << 21))
4434 /* An X_MASK with the RA/VA field fixed. */
4435 #define XRA_MASK (X_MASK | RA_MASK)
4442 /* An X_MASK with the RB field fixed. */
4443 #define XRB_MASK (X_MASK | RB_MASK)
4445 /* An X_MASK with the RT field fixed. */
4446 #define XRT_MASK (X_MASK | RT_MASK)
4454 /* An X_MASK with the RA and RB fields fixed. */
4455 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
4466 /* An X_MASK with the RT and RA fields fixed. */
4467 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
4469 /* An X_MASK with the RT and RB fields fixed. */
4470 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
4475 /* An X_MASK with the RT, RA and RB fields fixed. */
4476 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
4524 #define XCMP_MASK (X_MASK | (((uint64_t)1) << 22))
4534 #define XTO_MASK (X_MASK | TO_MASK)
4540 #define XTLB_MASK (X_MASK | SH_MASK)
4565 /* An X_MASK, but with the EH bit clear. */
4566 #define XEH_MASK (X_MASK & ~((uint64_t )1))
4652 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
4665 #define XSPR_MASK (X_MASK | SPR_MASK)
4866 {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
4937 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
4938 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5026 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5028 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5078 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5080 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5094 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5095 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5400 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5402 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
5440 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
5441 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
6437 {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
6879 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
6880 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
6882 {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
6883 {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
6908 {"isellt", XISEL(31,15,0), X_MASK, PPCISEL, EXT, {RT, RA0, RB}},
6909 {"iselgt", XISEL(31,15,1), X_MASK, PPCISEL, EXT, {RT, RA0, RB}},
6910 {"iseleq", XISEL(31,15,2), X_MASK, PPCISEL, EXT, {RT, RA0, RB}},
6916 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
6923 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
6925 {"icbt", X(31,22), X_MASK, POWER5|BOOKE|PPCE300, 0, {CT, RA0, RB}},
6927 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
6928 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
6930 {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6931 {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6932 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6933 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6940 {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6941 {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
6943 {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
6944 {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
6946 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
6947 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
6949 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
6957 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
6964 {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
6965 {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
6970 {"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}},
6972 {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
6988 {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
6992 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
6996 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
6997 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
7002 {"cntlzdm", X(31,59), X_MASK, POWER10, 0, {RA, RS, RB}},
7004 {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
7005 {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
7028 {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
7038 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
7039 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
7054 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
7056 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7060 {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7072 {"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}},
7084 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
7088 {"not", XRC(31,124,0), X_MASK, COM, EXT, {RA, RSB}},
7089 {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
7090 {"not.", XRC(31,124,1), X_MASK, COM, EXT, {RA, RSB}},
7091 {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
7099 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7101 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7119 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
7128 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
7129 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
7131 {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
7133 {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
7135 {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
7136 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
7138 {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
7139 {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
7141 {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
7142 {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
7147 {"pdepd", X(31,156), X_MASK, POWER10, 0, {RA, RS, RB}},
7149 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7151 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7155 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7157 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7165 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
7176 {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
7178 {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
7180 {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}},
7181 {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
7183 {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
7184 {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
7186 {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
7187 {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
7192 {"pextd", X(31,188), X_MASK, POWER10, 0, {RA, RS, RB}},
7196 {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
7198 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7220 {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
7222 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
7224 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
7226 {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
7228 {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
7229 {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
7231 {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
7232 {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
7235 {"cfuged", X(31,220), X_MASK, POWER10, 0, {RA, RS, RB}},
7237 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7241 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7243 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
7266 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
7276 {"dcbtstct", X(31,246), X_MASK, POWER4, EXT, {RA0, RB, THCT}},
7277 {"dcbtstds", X(31,246), X_MASK, POWER4, EXT, {RA0, RB, THDS}},
7278 {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
7279 {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
7280 {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
7282 {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
7284 {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
7285 {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
7287 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
7289 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7291 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
7292 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
7294 {"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}},
7298 {"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}},
7304 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
7311 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
7318 {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, 0, {RB, RSO, RIC, PRS, X_R}},
7321 {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
7325 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
7326 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
7330 {"dcbtct", X(31,278), X_MASK, POWER4, EXT, {RA0, RB, THCT}},
7331 {"dcbtds", X(31,278), X_MASK, POWER4, EXT, {RA0, RB, THDS}},
7332 {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
7333 {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
7334 {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
7336 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
7340 {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
7341 {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
7343 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7345 {"mfdcrux", X(31,291), X_MASK, PPC464|PPC476, 0, {RS, RA}},
7347 {"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}},
7348 {"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}},
7352 {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
7354 {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
7361 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
7363 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
7367 {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
7368 {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
7370 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
7406 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
7407 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
7409 {"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}},
7411 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
7420 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
7421 {"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}},
7490 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, EXT, {RT, TBR}},
7723 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
7725 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
7730 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
7732 {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
7745 {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
7748 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
7753 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
7759 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
7760 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
7762 {"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}},
7764 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
7775 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
7781 {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
7783 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
7784 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
7786 {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
7788 {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
7789 {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
7791 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
7795 {"mtdcrux", X(31,419), X_MASK, PPC464|PPC476, 0, {RA, RS}},
7797 {"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}},
7799 {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
7814 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
7816 {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
7840 {"mr", XRC(31,444,0), X_MASK, COM, EXT, {RA, RSB}},
7841 {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
7842 {"mr.", XRC(31,444,1), X_MASK, COM, EXT, {RA, RSB}},
7843 {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
7881 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
7882 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
7884 {"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}},
7897 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
7898 {"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}},
8159 {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
8163 {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
8164 {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
8170 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}},
8172 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
8174 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
8185 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
8194 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
8198 {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
8199 {"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
8201 {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
8203 {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
8222 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
8224 {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
8225 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
8227 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
8228 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
8230 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
8232 {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
8233 {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
8234 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
8235 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
8237 {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
8238 {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
8243 {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
8244 {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
8246 {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
8247 {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
8249 {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
8250 {"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
8252 {"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}},
8254 {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
8256 {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
8266 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
8271 {"cnttzdm", X(31,571), X_MASK, POWER10, 0, {RA, RS, RB}},
8275 {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
8276 {"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}},
8278 {"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}},
8280 {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
8288 {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
8289 {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
8307 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
8310 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
8312 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
8314 {"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}},
8316 {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
8326 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
8330 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
8332 {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
8333 {"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
8335 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
8356 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
8358 {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
8359 {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
8361 {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
8362 {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
8364 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
8366 {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
8367 {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
8369 {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
8370 {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
8372 {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
8373 {"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
8375 {"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}},
8377 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
8385 {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
8387 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
8389 {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
8390 {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
8392 {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
8393 {"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}},
8395 {"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}},
8397 {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
8417 {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
8418 {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
8420 {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
8422 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
8424 {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
8425 {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
8427 {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
8428 {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
8431 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
8433 {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
8435 {"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}},
8437 {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
8470 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
8472 {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
8473 {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
8475 {"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}},
8479 {"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}},
8480 {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
8491 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
8492 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
8497 {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
8501 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
8503 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
8505 {"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
8506 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
8508 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
8509 {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
8510 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
8511 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
8513 {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
8514 {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
8517 {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
8519 {"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}},
8520 {"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}},
8521 {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
8526 {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
8528 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
8530 {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
8532 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
8537 {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
8539 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
8540 {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
8541 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
8542 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
8547 {"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}},
8557 {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
8567 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
8570 {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
8574 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
8576 {"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}},
8586 {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
8590 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
8594 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
8602 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
8615 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
8616 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
8621 {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
8623 {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
8625 {"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
8626 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
8628 {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
8629 {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
8631 {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
8632 {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
8640 {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
8642 {"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}},
8646 {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
8648 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
8662 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
8664 {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
8666 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
8667 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
8669 {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
8671 {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
8672 {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
8677 {"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}},
8694 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
8698 {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
8702 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
8709 {"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}},
8728 {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
8804 {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8805 {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8850 {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8851 {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8874 {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
8879 {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
8897 {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8898 {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8900 {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8901 {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8903 {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
8904 {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
8910 {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8911 {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8923 {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8924 {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8926 {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8927 {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8933 {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
8935 {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
8936 {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
8942 {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8943 {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
8945 {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
8946 {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
8948 {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
8949 {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
8956 {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
8957 {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
9194 {"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9195 {"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9200 {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9201 {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9206 {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
9207 {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
9280 {"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9281 {"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9286 {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9287 {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9305 {"xscmpeqqp", X(63,68), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9319 {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9323 {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
9342 {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
9348 {"xscmpgeqp", X(63,196), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9355 {"xscmpgtqp", X(63,228), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9357 {"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
9358 {"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
9363 {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
9364 {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
9366 {"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
9367 {"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
9369 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
9370 {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
9372 {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9373 {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9378 {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9379 {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9384 {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9385 {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9390 {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9391 {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9396 {"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9397 {"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9399 {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9400 {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9402 {"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9403 {"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
9405 {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9406 {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9418 {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
9422 {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
9423 {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
9425 {"xsmaxcqp", X(63,676), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9427 {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
9434 {"xsmincqp", X(63,740), X_MASK, POWER10, PPCVLE, {VD, VA, VB}},
9436 {"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
9437 {"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
9439 {"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
9440 {"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}},
9460 {"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
9461 {"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
9477 {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
9484 {"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
9485 {"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
9487 {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
9495 {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
10455 {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
10457 {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},