Lines Matching defs:VX_MASK
3824 #define VX_MASK_DDD (VX_MASK & ~0x1)
4180 #define VX_MASK VX(0x3f, 0x7ff)
4249 /* A VX_MASK with the VA field fixed. */
4250 #define VXVA_MASK (VX_MASK | (0x1f << 16))
4252 /* A VX_MASK with the VB field fixed. */
4253 #define VXVB_MASK (VX_MASK | (0x1f << 11))
4255 /* A VX_MASK with the VA and VB fields fixed. */
4256 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
4258 /* A VX_MASK with the VD and VA fields fixed. */
4259 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
4261 /* A VX_MASK with a UIMM4 field. */
4262 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
4264 /* A VX_MASK with a UIMM3 field. */
4265 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
4267 /* A VX_MASK with a UIMM2 field. */
4268 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
4270 /* A VX_MASK with a PS field. */
4271 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
4273 /* A VX_MASK with the VA field fixed with a PS field. */
4276 /* A VX_MASK with the VA field fixed with a MP field. */
4279 /* A VX_MASK for instructions using a BF field. */
4280 #define VXBF_MASK (VX_MASK | (3 << 21))
4282 /* A VX_MASK for instructions with an RC field. */
4283 #define VXRC_MASK (VX_MASK & ~(0x1f << 6))
4285 /* A VX_MASK for instructions with a SH field. */
4286 #define VXSH_MASK (VX_MASK & ~(0x7 << 6))
4918 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4920 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4921 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4922 {"vrlq", VX (4, 5), VX_MASK, POWER10, 0, {VD, VA, VB}},
4925 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4926 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4927 {"vdivuq", VX (4, 11), VX_MASK, POWER10, 0, {VD, VA, VB}},
4929 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4935 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4936 {"vinsbvlx", VX (4, 15), VX_MASK, POWER10, 0, {VD, RA, VB}},
5011 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5012 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5013 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5014 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5015 {"vrlqmi", VX (4, 69), VX_MASK, POWER10, 0, {VD, VA, VB}},
5018 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5019 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5021 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5023 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5024 {"vinshvlx", VX (4, 79), VX_MASK, POWER10, 0, {VD, RA, VB}},
5034 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5035 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5036 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5037 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5040 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5041 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5042 {"vdivuw", VX (4, 139), VX_MASK, POWER10, 0, {VD, VA, VB}},
5043 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5044 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5045 {"vinswvlx", VX (4, 143), VX_MASK, POWER10, 0, {VD, RA, VB}},
5051 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5052 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5053 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5054 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5057 {"vmuloud", VX (4, 200), VX_MASK, POWER10, 0, {VD, VA, VB}},
5058 {"vdivud", VX (4, 203), VX_MASK, POWER10, 0, {VD, VA, VB}},
5059 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5065 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5067 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5068 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5069 {"vslq", VX (4, 261), VX_MASK, POWER10, 0, {VD, VA, VB}},
5071 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5073 {"vdivsq", VX (4, 267), VX_MASK, POWER10, 0, {VD, VA, VB}},
5074 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5075 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5076 {"vinsbvrx", VX (4, 271), VX_MASK, POWER10, 0, {VD, RA, VB}},
5083 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5085 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5086 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5087 {"vrlqnm", VX (4, 325), VX_MASK, POWER10, 0, {VD, VA, VB}},
5089 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5091 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5092 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5093 {"vinshvrx", VX (4, 335), VX_MASK, POWER10, 0, {VD, RA, VB}},
5100 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5101 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5102 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5103 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5105 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5107 {"vdivsw", VX (4, 395), VX_MASK, POWER10, 0, {VD, VA, VB}},
5108 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5109 {"vclrlb", VX (4, 397), VX_MASK, POWER10, 0, {VD, VA, RB}},
5110 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5111 {"vinswvrx", VX (4, 399), VX_MASK, POWER10, 0, {VD, RA, VB}},
5114 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5115 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5116 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5119 {"vmulosd", VX (4, 456), VX_MASK, POWER10, 0, {VD, VA, VB}},
5120 {"vmulld", VX (4, 457), VX_MASK, POWER10, 0, {VD, VA, VB}},
5122 {"vdivsd", VX (4, 459), VX_MASK, POWER10, 0, {VD, VA, VB}},
5123 {"vclrrb", VX (4, 461), VX_MASK, POWER10, 0, {VD, VA, RB}},
5124 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5130 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5131 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5133 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
5134 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5135 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5136 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
5137 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5138 {"vsrq", VX (4, 517), VX_MASK, POWER10, 0, {VD, VA, VB}},
5139 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
5140 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
5142 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
5143 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5144 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
5145 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
5147 {"vdiveuq", VX (4, 523), VX_MASK, POWER10, 0, {VD, VA, VB}},
5148 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
5149 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
5152 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
5153 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
5155 {"vinsblx", VX (4, 527), VX_MASK, POWER10, 0, {VD, RA, RB}},
5156 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5159 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5160 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5162 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5163 {"evmr", VX (4, 535), VX_MASK, PPCSPE, EXT, {RS, RAB}},
5164 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5165 {"evnot", VX (4, 536), VX_MASK, PPCSPE, EXT, {RS, RAB}},
5166 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5168 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5169 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5170 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5171 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5172 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5173 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
5174 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
5175 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5176 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
5177 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5178 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
5179 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
5180 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
5181 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5182 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5183 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5184 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5185 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5186 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5187 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5188 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5189 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5191 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5192 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5193 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5194 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5196 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5201 {"vinshlx", VX (4, 591), VX_MASK, POWER10, 0, {VD, RA, RB}},
5205 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5206 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5207 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5208 {"evfsmadd", VX (4, 642), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5209 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5210 {"evfsmsub", VX (4, 643), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5211 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
5212 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5213 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
5214 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
5218 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5219 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5220 {"vmulhuw", VX (4, 649), VX_MASK, POWER10, 0, {VD, VA, VB}},
5221 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5222 {"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5224 {"vdiveuw", VX (4, 651), VX_MASK, POWER10, 0, {VD, VA, VB}},
5225 {"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5226 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5229 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5230 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5232 {"vinswlx", VX (4, 655), VX_MASK, POWER10, 0, {VD, RA, RB}},
5233 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
5235 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
5236 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
5237 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
5238 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
5240 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
5241 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
5242 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
5243 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
5245 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
5246 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5247 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5248 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
5249 {"evfsmax", VX (4, 672), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5250 {"evfsmin", VX (4, 673), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5251 {"evfsaddsub", VX (4, 674), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5252 {"evfssubadd", VX (4, 675), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5253 {"evfssum", VX (4, 676), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5254 {"evfsdiff", VX (4, 677), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5255 {"evfssumdiff", VX (4, 678), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5256 {"evfsdiffsum", VX (4, 679), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5257 {"evfsaddx", VX (4, 680), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5258 {"evfssubx", VX (4, 681), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5259 {"evfsaddsubx", VX (4, 682), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5260 {"evfssubaddx", VX (4, 683), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5261 {"evfsmulx", VX (4, 684), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5262 {"evfsmule", VX (4, 686), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5263 {"evfsmulo", VX (4, 687), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5264 {"efsmax", VX (4, 688), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5265 {"efsmin", VX (4, 689), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5266 {"efdmax", VX (4, 696), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5268 {"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
5269 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5270 {"evsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5271 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5272 {"evssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5273 {"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
5274 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5275 {"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
5276 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
5277 {"evsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
5278 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5279 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
5280 {"evsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
5281 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
5282 {"evsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
5286 {"vmuleud", VX (4, 712), VX_MASK, POWER10, 0, {VD, VA, VB}},
5287 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5288 {"evsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5289 {"vmulhud", VX (4, 713), VX_MASK, POWER10, 0, {VD, VA, VB}},
5290 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5291 {"evsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5292 {"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
5294 {"vdiveud", VX (4, 715), VX_MASK, POWER10, 0, {VD, VA, VB}},
5295 {"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
5296 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5297 {"evscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5299 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5300 {"evsgmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5301 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5302 {"evsgmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5304 {"vinsdlx", VX (4, 719), VX_MASK, POWER10, 0, {VD, RA, RB}},
5305 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
5306 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
5307 {"evscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
5309 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
5310 {"evscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
5311 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
5312 {"evscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
5313 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
5314 {"evscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
5315 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
5316 {"evsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
5318 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
5319 {"evsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
5320 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
5321 {"evsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
5322 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
5323 {"evsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
5324 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
5325 {"evsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
5327 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
5328 {"evsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
5329 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5330 {"evststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5331 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5332 {"evststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5333 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5334 {"evststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5335 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5336 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5337 {"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
5338 {"efdcfuid", VX (4, 738), VX_MASK, E500|E500MC,0, {RS, RB}},
5339 {"efdmsub", VX (4, 739), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
5340 {"efdcfsid", VX (4, 739), VX_MASK, E500|E500MC,0, {RS, RB}},
5341 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
5342 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
5343 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
5345 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5346 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
5347 {"efdnmadd", VX (4, 746), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
5348 {"efdctuidz", VX (4, 746), VX_MASK, E500|E500MC,0, {RS, RB}},
5349 {"efdnmsub", VX (4, 747), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
5350 {"efdctsidz", VX (4, 747), VX_MASK, E500|E500MC,0, {RS, RB}},
5351 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5352 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5353 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5354 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
5360 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
5361 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
5362 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
5364 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
5365 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
5366 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
5372 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5373 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5374 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
5375 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5376 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5377 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
5378 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5379 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5380 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
5381 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5382 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5383 {"vsraq", VX (4, 773), VX_MASK, POWER10, 0, {VD, VA, VB}},
5384 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
5386 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5387 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5388 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
5389 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
5390 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}},
5391 {"vdivesq", VX (4, 779), VX_MASK, POWER10, 0, {VD, VA, VB}},
5392 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5395 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
5396 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5397 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5398 {"vinsbrx", VX (4, 783), VX_MASK, POWER10, 0, {VD, RA, RB}},
5399 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
5401 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5403 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5404 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5405 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5406 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5407 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5409 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5411 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5412 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5413 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5414 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5415 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
5416 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5417 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
5418 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5419 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
5420 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5421 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5422 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5423 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5424 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5425 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5426 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5427 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
5428 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5429 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5430 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5431 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5433 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5434 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
5435 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}},
5439 {"vinshrx", VX (4, 847), VX_MASK, POWER10, 0, {VD, RA, RB}},
5446 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5447 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5448 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5451 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5452 {"vmulhsw", VX (4, 905), VX_MASK, POWER10, 0, {VD, VA, VB}},
5453 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
5454 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}},
5455 {"vdivesw", VX (4, 907), VX_MASK, POWER10, 0, {VD, VA, VB}},
5458 {"vinswrx", VX (4, 911), VX_MASK, POWER10, 0, {VD, RA, RB}},
5461 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5462 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5465 {"vmulesd", VX (4, 968), VX_MASK, POWER10, 0, {VD, VA, VB}},
5466 {"vmulhsd", VX (4, 969), VX_MASK, POWER10, 0, {VD, VA, VB}},
5467 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
5468 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}},
5469 {"vdivesd", VX (4, 971), VX_MASK, POWER10, 0, {VD, VA, VB}},
5472 {"vinsdrx", VX (4, 975), VX_MASK, POWER10, 0, {VD, RA, RB}},
5477 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5479 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5480 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5481 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5482 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5487 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5488 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5489 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5490 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5491 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5492 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5493 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5494 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5499 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5500 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5505 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5506 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5507 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5508 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5509 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5510 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5511 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5512 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5513 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5515 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5516 {"evmwlssf", VX (4,1091), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5517 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5518 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5523 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5524 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5525 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5526 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5527 {"evmwlsmf", VX (4,1099), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5528 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5529 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5530 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5531 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5532 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5533 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5535 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5537 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5538 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5543 {"evmwlssfa", VX (4,1123), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5544 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5545 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5546 {"evmwlsmfa", VX (4,1131), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5547 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5548 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5549 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5550 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5551 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5552 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5553 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5554 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5555 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5556 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5557 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5558 {"vmr", VX (4,1156), VX_MASK, PPCVEC, EXT, {VD, VAB}},
5559 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5561 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5569 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5570 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
5572 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
5573 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
5574 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
5575 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
5576 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5577 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5582 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5583 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5584 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
5585 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
5586 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
5587 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
5588 {"vgnb", VX (4,1228), VX_MASK, POWER10, 0, {RT, VB, UIMM3}},
5589 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5596 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5597 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5599 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5600 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5601 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5602 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5603 {"vnot", VX (4,1284), VX_MASK, PPCVEC, EXT, {VD, VAB}},
5604 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5605 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5609 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5610 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5611 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5612 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5613 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5614 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5616 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5617 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5618 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5621 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5622 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5623 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5624 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5625 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5626 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5627 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5628 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5629 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5630 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5631 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5632 {"evmwlssfaaw", VX (4,1347), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5633 {"evmwhusiaa", VX (4,1348), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5634 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5635 {"evmwhssmaa", VX (4,1349), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5639 {"evmwhssfaa", VX (4,1351), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5640 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5641 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5642 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5643 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5644 {"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5645 {"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5646 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5647 {"vcfuged", VX (4,1357), VX_MASK, POWER10, 0, {VD, VA, VB}},
5648 {"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5649 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5650 {"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5651 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5653 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5655 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5656 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5659 {"evmwhgumiaa", VX (4,1380), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5660 {"evmwhgsmiaa", VX (4,1381), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5661 {"evmwhgssfaa", VX (4,1383), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5662 {"evmwhgsmfaa", VX (4,1391), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5663 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5664 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5665 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5673 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5674 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5675 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5676 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5677 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5681 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5682 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5683 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5684 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5685 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5686 {"vpextd", VX (4,1421), VX_MASK, POWER10, 0, {VD, VA, VB}},
5687 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5688 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5691 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5692 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5693 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5694 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5695 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5696 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5697 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5699 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5700 {"evmwlssfanw", VX (4,1475), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5701 {"evmwhusian", VX (4,1476), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5702 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5703 {"evmwhssian", VX (4,1477), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5708 {"evmwhssfan", VX (4,1479), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5710 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5711 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5712 {"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5713 {"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5714 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5715 {"vpdepd", VX (4,1485), VX_MASK, POWER10, 0, {VD, VA, VB}},
5716 {"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5717 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5718 {"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5719 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5721 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5723 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5724 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
5725 {"evmwhgumian", VX (4,1508), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5726 {"evmwhgsmian", VX (4,1509), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5727 {"evmwhgssfan", VX (4,1511), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5728 {"evmwhgsmfan", VX (4,1519), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
5731 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5753 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5754 {"vmoduq", VX (4,1547), VX_MASK, POWER10, 0, {VD, VA, VB}},
5755 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5756 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5780 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5783 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5785 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5786 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
5787 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5792 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5793 {"vmoduw", VX (4,1675), VX_MASK, POWER10, 0, {VD, VA, VB}},
5794 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5795 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5796 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
5797 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5802 {"vmodud", VX (4,1739), VX_MASK, POWER10, 0, {VD, VA, VB}},
5804 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5807 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5811 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5812 {"vmodsq", VX (4,1803), VX_MASK, POWER10, 0, {VD, VA, VB}},
5813 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5816 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5819 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
5821 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5828 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5831 {"vclzdm", VX (4,1924), VX_MASK, POWER10, 0, {VD, VA, VB}},
5836 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5837 {"vmodsw", VX (4,1931), VX_MASK, POWER10, 0, {VD, VA, VB}},
5838 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
5839 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
5844 {"vctzdm", VX (4,1988), VX_MASK, POWER10, 0, {VD, VA, VB}},
5849 {"vmodsd", VX (4,1995), VX_MASK, POWER10, 0, {VD, VA, VB}},
8516 {"evlddepx", VX (31, 1598), VX_MASK, PPCSPE, 0, {RT, RA, RB}},
8639 {"evstddepx", VX (31, 1854), VX_MASK, PPCSPE, 0, {RT, RA, RB}},
9626 {"zvaddih", VX(4, 0x200), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
9627 {"zvsubifh", VX(4, 0x201), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
9628 {"zvaddh", VX(4, 0x204), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9629 {"zvsubfh", VX(4, 0x205), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9630 {"zvaddsubfh", VX(4, 0x206), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9631 {"zvsubfaddh", VX(4, 0x207), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9632 {"zvaddhx", VX(4, 0x20C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9633 {"zvsubfhx", VX(4, 0x20D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9634 {"zvaddsubfhx", VX(4, 0x20E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9635 {"zvsubfaddhx", VX(4, 0x20F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9636 {"zaddwus", VX(4, 0x210), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9637 {"zsubfwus", VX(4, 0x211), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9638 {"zaddwss", VX(4, 0x212), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9639 {"zsubfwss", VX(4, 0x213), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9640 {"zvaddhus", VX(4, 0x214), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9641 {"zvsubfhus", VX(4, 0x215), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9642 {"zvaddhss", VX(4, 0x216), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9643 {"zvsubfhss", VX(4, 0x217), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9644 {"zvaddsubfhss", VX(4, 0x21A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9645 {"zvsubfaddhss", VX(4, 0x21B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9646 {"zvaddhxss", VX(4, 0x21C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9647 {"zvsubfhxss", VX(4, 0x21D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9648 {"zvaddsubfhxss", VX(4, 0x21E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9649 {"zvsubfaddhxss", VX(4, 0x21F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9650 {"zaddheuw", VX(4, 0x220), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9651 {"zsubfheuw", VX(4, 0x221), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9652 {"zaddhesw", VX(4, 0x222), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9653 {"zsubfhesw", VX(4, 0x223), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9654 {"zaddhouw", VX(4, 0x224), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9655 {"zsubfhouw", VX(4, 0x225), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9656 {"zaddhosw", VX(4, 0x226), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9657 {"zsubfhosw", VX(4, 0x227), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9658 {"zvmergehih", VX(4, 0x22C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9659 {"zvmergeloh", VX(4, 0x22D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9660 {"zvmergehiloh", VX(4, 0x22E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9661 {"zvmergelohih", VX(4, 0x22F), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9662 {"zvcmpgthu", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
9663 {"zvcmpgths", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
9664 {"zvcmplthu", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
9665 {"zvcmplths", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
9666 {"zvcmpeqh", VX(4, 0x232), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}},
9667 {"zpkswgshfrs", VX(4, 0x238), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9668 {"zpkswgswfrs", VX(4, 0x239), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9669 {"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9670 {"zvpkswshfrs", VX(4, 0x23B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9671 {"zvpkswuhs", VX(4, 0x23C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9672 {"zvpkswshs", VX(4, 0x23D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9673 {"zvpkuwuhs", VX(4, 0x23E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9698 {"zsatsduw", VX(4, 0x260), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9699 {"zsatsdsw", VX(4, 0x261), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9700 {"zsatuduw", VX(4, 0x262), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9701 {"zvselh", VX(4, 0x264), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9703 {"zbrminc", VX(4, 0x268), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9704 {"zcircinc", VX(4, 0x269), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9705 {"zdivwsf", VX(4, 0x26B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9706 {"zvsrhu", VX(4, 0x270), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9707 {"zvsrhs", VX(4, 0x271), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9708 {"zvsrhiu", VX(4, 0x272), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
9709 {"zvsrhis", VX(4, 0x273), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
9710 {"zvslh", VX(4, 0x274), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9711 {"zvrlh", VX(4, 0x275), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9712 {"zvslhi", VX(4, 0x276), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
9713 {"zvrlhi", VX(4, 0x277), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
9714 {"zvslhus", VX(4, 0x278), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9715 {"zvslhss", VX(4, 0x279), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9716 {"zvslhius", VX(4, 0x27A), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
9717 {"zvslhiss", VX(4, 0x27B), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}},
9718 {"zslwus", VX(4, 0x27C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9719 {"zslwss", VX(4, 0x27D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9720 {"zslwius", VX(4, 0x27E), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
9721 {"zslwiss", VX(4, 0x27F), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}},
9722 {"zaddwgui", VX(4, 0x460), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9723 {"zsubfwgui", VX(4, 0x461), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9724 {"zaddd", VX(4, 0x462), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9725 {"zsubfd", VX(4, 0x463), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9726 {"zvaddsubfw", VX(4, 0x464), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9727 {"zvsubfaddw", VX(4, 0x465), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9728 {"zvaddw", VX(4, 0x466), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9729 {"zvsubfw", VX(4, 0x467), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9730 {"zaddwgsi", VX(4, 0x468), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9731 {"zsubfwgsi", VX(4, 0x469), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9732 {"zadddss", VX(4, 0x46A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9733 {"zsubfdss", VX(4, 0x46B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9734 {"zvaddsubfwss", VX(4, 0x46C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9735 {"zvsubfaddwss", VX(4, 0x46D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9736 {"zvaddwss", VX(4, 0x46E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9737 {"zvsubfwss", VX(4, 0x46F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9738 {"zaddwgsf", VX(4, 0x470), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9739 {"zsubfwgsf", VX(4, 0x471), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9740 {"zadddus", VX(4, 0x472), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9741 {"zsubfdus", VX(4, 0x473), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9742 {"zvaddwus", VX(4, 0x476), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9743 {"zvsubfwus", VX(4, 0x477), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9749 {"zvdotphgwasmf", VX(4, 0x488), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9750 {"zvdotphgwasmfr", VX(4, 0x489), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9751 {"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9752 {"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9753 {"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9754 {"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9755 {"zvmhulgwsmf", VX(4, 0x490), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9756 {"zvmhulgwsmfr", VX(4, 0x491), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9757 {"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9758 {"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9759 {"zvmhulgwsmfan", VX(4, 0x494), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9760 {"zvmhulgwsmfran", VX(4, 0x495), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9761 {"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9762 {"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9763 {"zmhegwsmf", VX(4, 0x498), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9764 {"zmhegwsmfr", VX(4, 0x499), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9765 {"zmhegwsmfaa", VX(4, 0x49A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9766 {"zmhegwsmfraa", VX(4, 0x49B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9767 {"zmhegwsmfan", VX(4, 0x49C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9768 {"zmhegwsmfran", VX(4, 0x49D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9769 {"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9770 {"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9771 {"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9772 {"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9773 {"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9774 {"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9775 {"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9776 {"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9777 {"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9778 {"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9779 {"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9780 {"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9781 {"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9782 {"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9783 {"zmheogwsmf", VX(4, 0x4B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9784 {"zmheogwsmfr", VX(4, 0x4B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9785 {"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9786 {"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9787 {"zmheogwsmfan", VX(4, 0x4BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9788 {"zmheogwsmfran", VX(4, 0x4BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9789 {"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9790 {"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9791 {"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9792 {"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9793 {"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9794 {"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9795 {"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9796 {"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9797 {"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9798 {"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9799 {"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9800 {"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9801 {"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9802 {"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9803 {"zmhogwsmf", VX(4, 0x4D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9804 {"zmhogwsmfr", VX(4, 0x4D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9805 {"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9806 {"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9807 {"zmhogwsmfan", VX(4, 0x4DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9808 {"zmhogwsmfran", VX(4, 0x4DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
9809 {"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9810 {"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9811 {"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9812 {"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9813 {"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9814 {"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9815 {"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9816 {"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9817 {"zmhegui", VX(4, 0x500), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9818 {"zvdotphgaui", VX(4, 0x501), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9819 {"zmheguiaa", VX(4, 0x502), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9820 {"zvdotphgauiaa", VX(4, 0x503), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9821 {"zmheguian", VX(4, 0x504), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9822 {"zvdotphgauian", VX(4, 0x505), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9823 {"zmhegsi", VX(4, 0x508), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9824 {"zvdotphgasi", VX(4, 0x509), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9825 {"zmhegsiaa", VX(4, 0x50A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9826 {"zvdotphgasiaa", VX(4, 0x50B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9827 {"zmhegsian", VX(4, 0x50C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9828 {"zvdotphgasian", VX(4, 0x50D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9829 {"zmhegsui", VX(4, 0x510), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9830 {"zvdotphgasui", VX(4, 0x511), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9831 {"zmhegsuiaa", VX(4, 0x512), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9832 {"zvdotphgasuiaa", VX(4, 0x513), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9833 {"zmhegsuian", VX(4, 0x514), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9834 {"zvdotphgasuian", VX(4, 0x515), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9835 {"zmhegsmf", VX(4, 0x518), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9836 {"zvdotphgasmf", VX(4, 0x519), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9837 {"zmhegsmfaa", VX(4, 0x51A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9838 {"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9839 {"zmhegsmfan", VX(4, 0x51C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9840 {"zvdotphgasmfan", VX(4, 0x51D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9841 {"zmheogui", VX(4, 0x520), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9842 {"zvdotphxgaui", VX(4, 0x521), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9843 {"zmheoguiaa", VX(4, 0x522), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9844 {"zvdotphxgauiaa", VX(4, 0x523), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9845 {"zmheoguian", VX(4, 0x524), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9846 {"zvdotphxgauian", VX(4, 0x525), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9847 {"zmheogsi", VX(4, 0x528), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9848 {"zvdotphxgasi", VX(4, 0x529), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9849 {"zmheogsiaa", VX(4, 0x52A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9850 {"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9851 {"zmheogsian", VX(4, 0x52C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9852 {"zvdotphxgasian", VX(4, 0x52D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9853 {"zmheogsui", VX(4, 0x530), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9854 {"zvdotphxgasui", VX(4, 0x531), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9855 {"zmheogsuiaa", VX(4, 0x532), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9856 {"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9857 {"zmheogsuian", VX(4, 0x534), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9858 {"zvdotphxgasuian", VX(4, 0x535), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9859 {"zmheogsmf", VX(4, 0x538), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9860 {"zvdotphxgasmf", VX(4, 0x539), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9861 {"zmheogsmfaa", VX(4, 0x53A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9862 {"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9863 {"zmheogsmfan", VX(4, 0x53C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9864 {"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9865 {"zmhogui", VX(4, 0x540), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9866 {"zvdotphgsui", VX(4, 0x541), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9867 {"zmhoguiaa", VX(4, 0x542), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9868 {"zvdotphgsuiaa", VX(4, 0x543), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9869 {"zmhoguian", VX(4, 0x544), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9870 {"zvdotphgsuian", VX(4, 0x545), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9871 {"zmhogsi", VX(4, 0x548), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9872 {"zvdotphgssi", VX(4, 0x549), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9873 {"zmhogsiaa", VX(4, 0x54A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9874 {"zvdotphgssiaa", VX(4, 0x54B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9875 {"zmhogsian", VX(4, 0x54C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9876 {"zvdotphgssian", VX(4, 0x54D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9877 {"zmhogsui", VX(4, 0x550), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9878 {"zvdotphgssui", VX(4, 0x551), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9879 {"zmhogsuiaa", VX(4, 0x552), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9880 {"zvdotphgssuiaa", VX(4, 0x553), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9881 {"zmhogsuian", VX(4, 0x554), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9882 {"zvdotphgssuian", VX(4, 0x555), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9883 {"zmhogsmf", VX(4, 0x558), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9884 {"zvdotphgssmf", VX(4, 0x559), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9885 {"zmhogsmfaa", VX(4, 0x55A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9886 {"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9887 {"zmhogsmfan", VX(4, 0x55C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9888 {"zvdotphgssmfan", VX(4, 0x55D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9889 {"zmwgui", VX(4, 0x560), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9890 {"zmwguiaa", VX(4, 0x562), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9891 {"zmwguiaas", VX(4, 0x563), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9892 {"zmwguian", VX(4, 0x564), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9893 {"zmwguians", VX(4, 0x565), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9894 {"zmwgsi", VX(4, 0x568), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9895 {"zmwgsiaa", VX(4, 0x56A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9896 {"zmwgsiaas", VX(4, 0x56B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9897 {"zmwgsian", VX(4, 0x56C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9898 {"zmwgsians", VX(4, 0x56D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9899 {"zmwgsui", VX(4, 0x570), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9900 {"zmwgsuiaa", VX(4, 0x572), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9901 {"zmwgsuiaas", VX(4, 0x573), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9902 {"zmwgsuian", VX(4, 0x574), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9903 {"zmwgsuians", VX(4, 0x575), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9904 {"zmwgsmf", VX(4, 0x578), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9905 {"zmwgsmfr", VX(4, 0x579), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9906 {"zmwgsmfaa", VX(4, 0x57A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9907 {"zmwgsmfraa", VX(4, 0x57B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9908 {"zmwgsmfan", VX(4, 0x57C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9909 {"zmwgsmfran", VX(4, 0x57D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9910 {"zvmhului", VX(4, 0x580), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9911 {"zvmhuluiaa", VX(4, 0x582), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9912 {"zvmhuluiaas", VX(4, 0x583), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9913 {"zvmhuluian", VX(4, 0x584), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9914 {"zvmhuluians", VX(4, 0x585), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9915 {"zvmhuluianp", VX(4, 0x586), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9916 {"zvmhuluianps", VX(4, 0x587), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9917 {"zvmhulsi", VX(4, 0x588), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9918 {"zvmhulsiaa", VX(4, 0x58A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9919 {"zvmhulsiaas", VX(4, 0x58B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9920 {"zvmhulsian", VX(4, 0x58C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9921 {"zvmhulsians", VX(4, 0x58D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9922 {"zvmhulsianp", VX(4, 0x58E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9923 {"zvmhulsianps", VX(4, 0x58F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9924 {"zvmhulsui", VX(4, 0x590), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9925 {"zvmhulsuiaa", VX(4, 0x592), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9926 {"zvmhulsuiaas", VX(4, 0x593), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9927 {"zvmhulsuian", VX(4, 0x594), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9928 {"zvmhulsuians", VX(4, 0x595), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9929 {"zvmhulsuianp", VX(4, 0x596), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9930 {"zvmhulsuianps", VX(4, 0x597), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9931 {"zvmhulsf", VX(4, 0x598), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9932 {"zvmhulsfr", VX(4, 0x599), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9933 {"zvmhulsfaas", VX(4, 0x59A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9934 {"zvmhulsfraas", VX(4, 0x59B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9935 {"zvmhulsfans", VX(4, 0x59C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9936 {"zvmhulsfrans", VX(4, 0x59D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9937 {"zvmhulsfanps", VX(4, 0x59E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9938 {"zvmhulsfranps", VX(4, 0x59F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9939 {"zvmhllui", VX(4, 0x5A0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9940 {"zvmhlluiaa", VX(4, 0x5A2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9941 {"zvmhlluiaas", VX(4, 0x5A3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9942 {"zvmhlluian", VX(4, 0x5A4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9943 {"zvmhlluians", VX(4, 0x5A5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9944 {"zvmhlluianp", VX(4, 0x5A6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9945 {"zvmhlluianps", VX(4, 0x5A7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9946 {"zvmhllsi", VX(4, 0x5A8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9947 {"zvmhllsiaa", VX(4, 0x5AA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9948 {"zvmhllsiaas", VX(4, 0x5AB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9949 {"zvmhllsian", VX(4, 0x5AC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9950 {"zvmhllsians", VX(4, 0x5AD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9951 {"zvmhllsianp", VX(4, 0x5AE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9952 {"zvmhllsianps", VX(4, 0x5AF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9953 {"zvmhllsui", VX(4, 0x5B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9954 {"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9955 {"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9956 {"zvmhllsuian", VX(4, 0x5B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9957 {"zvmhllsuians", VX(4, 0x5B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9958 {"zvmhllsuianp", VX(4, 0x5B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9959 {"zvmhllsuianps", VX(4, 0x5B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9960 {"zvmhllsf", VX(4, 0x5B8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9961 {"zvmhllsfr", VX(4, 0x5B9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9962 {"zvmhllsfaas", VX(4, 0x5BA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9963 {"zvmhllsfraas", VX(4, 0x5BB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9964 {"zvmhllsfans", VX(4, 0x5BC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9965 {"zvmhllsfrans", VX(4, 0x5BD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9966 {"zvmhllsfanps", VX(4, 0x5BE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9967 {"zvmhllsfranps", VX(4, 0x5BF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9968 {"zvmhuuui", VX(4, 0x5C0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9969 {"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9970 {"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9971 {"zvmhuuuian", VX(4, 0x5C4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9972 {"zvmhuuuians", VX(4, 0x5C5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9973 {"zvmhuuuianp", VX(4, 0x5C6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9974 {"zvmhuuuianps", VX(4, 0x5C7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9975 {"zvmhuusi", VX(4, 0x5C8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9976 {"zvmhuusiaa", VX(4, 0x5CA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9977 {"zvmhuusiaas", VX(4, 0x5CB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9978 {"zvmhuusian", VX(4, 0x5CC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9979 {"zvmhuusians", VX(4, 0x5CD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9980 {"zvmhuusianp", VX(4, 0x5CE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9981 {"zvmhuusianps", VX(4, 0x5CF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9982 {"zvmhuusui", VX(4, 0x5D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9983 {"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9984 {"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9985 {"zvmhuusuian", VX(4, 0x5D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9986 {"zvmhuusuians", VX(4, 0x5D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9987 {"zvmhuusuianp", VX(4, 0x5D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9988 {"zvmhuusuianps", VX(4, 0x5D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9989 {"zvmhuusf", VX(4, 0x5D8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9990 {"zvmhuusfr", VX(4, 0x5D9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9991 {"zvmhuusfaas", VX(4, 0x5DA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9992 {"zvmhuusfraas", VX(4, 0x5DB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9993 {"zvmhuusfans", VX(4, 0x5DC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9994 {"zvmhuusfrans", VX(4, 0x5DD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9995 {"zvmhuusfanps", VX(4, 0x5DE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9996 {"zvmhuusfranps", VX(4, 0x5DF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9997 {"zvmhxlui", VX(4, 0x5E0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9998 {"zvmhxluiaa", VX(4, 0x5E2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
9999 {"zvmhxluiaas", VX(4, 0x5E3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10000 {"zvmhxluian", VX(4, 0x5E4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10001 {"zvmhxluians", VX(4, 0x5E5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10002 {"zvmhxluianp", VX(4, 0x5E6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10003 {"zvmhxluianps", VX(4, 0x5E7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10004 {"zvmhxlsi", VX(4, 0x5E8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10005 {"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10006 {"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10007 {"zvmhxlsian", VX(4, 0x5EC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10008 {"zvmhxlsians", VX(4, 0x5ED), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10009 {"zvmhxlsianp", VX(4, 0x5EE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10010 {"zvmhxlsianps", VX(4, 0x5EF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10011 {"zvmhxlsui", VX(4, 0x5F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10012 {"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10013 {"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10014 {"zvmhxlsuian", VX(4, 0x5F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10015 {"zvmhxlsuians", VX(4, 0x5F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10016 {"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10017 {"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10018 {"zvmhxlsf", VX(4, 0x5F8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10019 {"zvmhxlsfr", VX(4, 0x5F9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10020 {"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10021 {"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10022 {"zvmhxlsfans", VX(4, 0x5FC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10023 {"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10024 {"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10025 {"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10026 {"zmheui", VX(4, 0x600), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10027 {"zmheuiaa", VX(4, 0x602), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10028 {"zmheuiaas", VX(4, 0x603), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10029 {"zmheuian", VX(4, 0x604), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10030 {"zmheuians", VX(4, 0x605), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10031 {"zmhesi", VX(4, 0x608), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10032 {"zmhesiaa", VX(4, 0x60A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10033 {"zmhesiaas", VX(4, 0x60B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10034 {"zmhesian", VX(4, 0x60C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10035 {"zmhesians", VX(4, 0x60D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10036 {"zmhesui", VX(4, 0x610), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10037 {"zmhesuiaa", VX(4, 0x612), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10038 {"zmhesuiaas", VX(4, 0x613), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10039 {"zmhesuian", VX(4, 0x614), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10040 {"zmhesuians", VX(4, 0x615), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10041 {"zmhesf", VX(4, 0x618), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10042 {"zmhesfr", VX(4, 0x619), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10043 {"zmhesfaas", VX(4, 0x61A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10044 {"zmhesfraas", VX(4, 0x61B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10045 {"zmhesfans", VX(4, 0x61C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10046 {"zmhesfrans", VX(4, 0x61D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10047 {"zmheoui", VX(4, 0x620), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10048 {"zmheouiaa", VX(4, 0x622), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10049 {"zmheouiaas", VX(4, 0x623), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10050 {"zmheouian", VX(4, 0x624), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10051 {"zmheouians", VX(4, 0x625), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10052 {"zmheosi", VX(4, 0x628), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10053 {"zmheosiaa", VX(4, 0x62A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10054 {"zmheosiaas", VX(4, 0x62B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10055 {"zmheosian", VX(4, 0x62C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10056 {"zmheosians", VX(4, 0x62D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10057 {"zmheosui", VX(4, 0x630), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10058 {"zmheosuiaa", VX(4, 0x632), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10059 {"zmheosuiaas", VX(4, 0x633), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10060 {"zmheosuian", VX(4, 0x634), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10061 {"zmheosuians", VX(4, 0x635), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10062 {"zmheosf", VX(4, 0x638), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10063 {"zmheosfr", VX(4, 0x639), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10064 {"zmheosfaas", VX(4, 0x63A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10065 {"zmheosfraas", VX(4, 0x63B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10066 {"zmheosfans", VX(4, 0x63C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10067 {"zmheosfrans", VX(4, 0x63D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10068 {"zmhoui", VX(4, 0x640), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10069 {"zmhouiaa", VX(4, 0x642), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10070 {"zmhouiaas", VX(4, 0x643), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10071 {"zmhouian", VX(4, 0x644), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10072 {"zmhouians", VX(4, 0x645), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10073 {"zmhosi", VX(4, 0x648), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10074 {"zmhosiaa", VX(4, 0x64A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10075 {"zmhosiaas", VX(4, 0x64B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10076 {"zmhosian", VX(4, 0x64C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10077 {"zmhosians", VX(4, 0x64D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10078 {"zmhosui", VX(4, 0x650), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10079 {"zmhosuiaa", VX(4, 0x652), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10080 {"zmhosuiaas", VX(4, 0x653), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10081 {"zmhosuian", VX(4, 0x654), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10082 {"zmhosuians", VX(4, 0x655), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10083 {"zmhosf", VX(4, 0x658), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10084 {"zmhosfr", VX(4, 0x659), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10085 {"zmhosfaas", VX(4, 0x65A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10086 {"zmhosfraas", VX(4, 0x65B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10087 {"zmhosfans", VX(4, 0x65C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10088 {"zmhosfrans", VX(4, 0x65D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10089 {"zvmhuih", VX(4, 0x660), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10090 {"zvmhuihs", VX(4, 0x661), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10091 {"zvmhuiaah", VX(4, 0x662), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10092 {"zvmhuiaahs", VX(4, 0x663), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10093 {"zvmhuianh", VX(4, 0x664), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10094 {"zvmhuianhs", VX(4, 0x665), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10095 {"zvmhsihs", VX(4, 0x669), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10096 {"zvmhsiaahs", VX(4, 0x66B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10097 {"zvmhsianhs", VX(4, 0x66D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10098 {"zvmhsuihs", VX(4, 0x671), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10099 {"zvmhsuiaahs", VX(4, 0x673), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10100 {"zvmhsuianhs", VX(4, 0x675), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10101 {"zvmhsfh", VX(4, 0x678), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10102 {"zvmhsfrh", VX(4, 0x679), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10103 {"zvmhsfaahs", VX(4, 0x67A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10104 {"zvmhsfraahs", VX(4, 0x67B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10105 {"zvmhsfanhs", VX(4, 0x67C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10106 {"zvmhsfranhs", VX(4, 0x67D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10107 {"zvdotphaui", VX(4, 0x680), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10108 {"zvdotphauis", VX(4, 0x681), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10109 {"zvdotphauiaa", VX(4, 0x682), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10110 {"zvdotphauiaas", VX(4, 0x683), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10111 {"zvdotphauian", VX(4, 0x684), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10112 {"zvdotphauians", VX(4, 0x685), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10113 {"zvdotphasi", VX(4, 0x688), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10114 {"zvdotphasis", VX(4, 0x689), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10115 {"zvdotphasiaa", VX(4, 0x68A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10116 {"zvdotphasiaas", VX(4, 0x68B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10117 {"zvdotphasian", VX(4, 0x68C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10118 {"zvdotphasians", VX(4, 0x68D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10119 {"zvdotphasui", VX(4, 0x690), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10120 {"zvdotphasuis", VX(4, 0x691), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10121 {"zvdotphasuiaa", VX(4, 0x692), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10122 {"zvdotphasuiaas", VX(4, 0x693), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10123 {"zvdotphasuian", VX(4, 0x694), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10124 {"zvdotphasuians", VX(4, 0x695), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10125 {"zvdotphasfs", VX(4, 0x698), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10126 {"zvdotphasfrs", VX(4, 0x699), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10127 {"zvdotphasfaas", VX(4, 0x69A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10128 {"zvdotphasfraas", VX(4, 0x69B), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10129 {"zvdotphasfans", VX(4, 0x69C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10130 {"zvdotphasfrans", VX(4, 0x69D), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10131 {"zvdotphxaui", VX(4, 0x6A0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10132 {"zvdotphxauis", VX(4, 0x6A1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10133 {"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10134 {"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10135 {"zvdotphxauian", VX(4, 0x6A4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10136 {"zvdotphxauians", VX(4, 0x6A5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10137 {"zvdotphxasi", VX(4, 0x6A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10138 {"zvdotphxasis", VX(4, 0x6A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10139 {"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10140 {"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10141 {"zvdotphxasian", VX(4, 0x6AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10142 {"zvdotphxasians", VX(4, 0x6AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10143 {"zvdotphxasui", VX(4, 0x6B0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10144 {"zvdotphxasuis", VX(4, 0x6B1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10145 {"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10146 {"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10147 {"zvdotphxasuian", VX(4, 0x6B4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10148 {"zvdotphxasuians", VX(4, 0x6B5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10149 {"zvdotphxasfs", VX(4, 0x6B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10150 {"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10151 {"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10152 {"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10153 {"zvdotphxasfans", VX(4, 0x6BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10154 {"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10155 {"zvdotphsui", VX(4, 0x6C0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10156 {"zvdotphsuis", VX(4, 0x6C1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10157 {"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10158 {"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10159 {"zvdotphsuian", VX(4, 0x6C4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10160 {"zvdotphsuians", VX(4, 0x6C5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10161 {"zvdotphssi", VX(4, 0x6C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10162 {"zvdotphssis", VX(4, 0x6C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10163 {"zvdotphssiaa", VX(4, 0x6CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10164 {"zvdotphssiaas", VX(4, 0x6CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10165 {"zvdotphssian", VX(4, 0x6CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10166 {"zvdotphssians", VX(4, 0x6CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10167 {"zvdotphssui", VX(4, 0x6D0), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10168 {"zvdotphssuis", VX(4, 0x6D1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10169 {"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10170 {"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10171 {"zvdotphssuian", VX(4, 0x6D4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10172 {"zvdotphssuians", VX(4, 0x6D5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10173 {"zvdotphssfs", VX(4, 0x6D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10174 {"zvdotphssfrs", VX(4, 0x6D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10175 {"zvdotphssfaas", VX(4, 0x6DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10176 {"zvdotphssfraas", VX(4, 0x6DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10177 {"zvdotphssfans", VX(4, 0x6DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10178 {"zvdotphssfrans", VX(4, 0x6DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10179 {"zmwluis", VX(4, 0x6E1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10180 {"zmwluiaa", VX(4, 0x6E2), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10181 {"zmwluiaas", VX(4, 0x6E3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10182 {"zmwluian", VX(4, 0x6E4), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10183 {"zmwluians", VX(4, 0x6E5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10184 {"zmwlsis", VX(4, 0x6E9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10185 {"zmwlsiaas", VX(4, 0x6EB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10186 {"zmwlsians", VX(4, 0x6ED), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10187 {"zmwlsuis", VX(4, 0x6F1), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10188 {"zmwlsuiaas", VX(4, 0x6F3), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10189 {"zmwlsuians", VX(4, 0x6F5), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10190 {"zmwsf", VX(4, 0x6F8), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10191 {"zmwsfr", VX(4, 0x6F9), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10192 {"zmwsfaas", VX(4, 0x6FA), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10193 {"zmwsfraas", VX(4, 0x6FB), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10194 {"zmwsfans", VX(4, 0x6FC), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10195 {"zmwsfrans", VX(4, 0x6FD), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10196 {"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10197 {"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
10198 {"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10199 {"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
10200 {"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10201 {"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}},
10202 {"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10203 {"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10204 {"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10205 {"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10206 {"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10207 {"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10208 {"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10209 {"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10210 {"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10211 {"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10212 {"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10213 {"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10214 {"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10215 {"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10216 {"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10217 {"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}},
10218 {"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10219 {"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
10220 {"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10221 {"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}},
10222 {"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10223 {"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
10224 {"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10225 {"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
10226 {"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10227 {"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
10228 {"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10229 {"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
10230 {"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10231 {"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}},
10232 {"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10233 {"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
10234 {"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10235 {"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}},
10236 {"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10237 {"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
10238 {"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10239 {"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
10240 {"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10241 {"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}},
10242 {"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10243 {"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
10244 {"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10245 {"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}},
10246 {"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10247 {"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
10248 {"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10249 {"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}},
10250 {"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10251 {"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
10252 {"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10253 {"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
10254 {"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10255 {"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}},
10256 {"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10257 {"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10258 {"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10259 {"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10260 {"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10261 {"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10262 {"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10263 {"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10264 {"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10265 {"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10266 {"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10267 {"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10268 {"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10269 {"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10270 {"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}},
10271 {"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}},
10272 {"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10273 {"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
10274 {"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10275 {"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}},
10276 {"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10277 {"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
10278 {"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10279 {"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
10280 {"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10281 {"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}},
10282 {"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10283 {"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
10284 {"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10285 {"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}},
10286 {"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10287 {"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
10288 {"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}},
10289 {"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}},
10290 {"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10291 {"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
10292 {"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10293 {"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
10294 {"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}},
10295 {"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}},
10296 {"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10297 {"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
10298 {"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10299 {"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}},
10300 {"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10301 {"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
10302 {"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}},
10303 {"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}},
10525 {"evdotpwcssi", VX (4, 128), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10526 {"evdotpwcsmi", VX (4, 129), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10527 {"evdotpwcssfr", VX (4, 130), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10528 {"evdotpwcssf", VX (4, 131), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10529 {"evdotpwgasmf", VX (4, 136), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10530 {"evdotpwxgasmf", VX (4, 137), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10531 {"evdotpwgasmfr", VX (4, 138), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10532 {"evdotpwxgasmfr", VX (4, 139), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10533 {"evdotpwgssmf", VX (4, 140), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10534 {"evdotpwxgssmf", VX (4, 141), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10535 {"evdotpwgssmfr", VX (4, 142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10536 {"evdotpwxgssmfr", VX (4, 143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10537 {"evdotpwcssiaaw3", VX (4, 144), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10538 {"evdotpwcsmiaaw3", VX (4, 145), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10539 {"evdotpwcssfraaw3", VX (4, 146), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10540 {"evdotpwcssfaaw3", VX (4, 147), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10541 {"evdotpwgasmfaa3", VX (4, 152), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10542 {"evdotpwxgasmfaa3", VX (4, 153), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10543 {"evdotpwgasmfraa3", VX (4, 154), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10544 {"evdotpwxgasmfraa3", VX (4, 155), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10545 {"evdotpwgssmfaa3", VX (4, 156), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10546 {"evdotpwxgssmfaa3", VX (4, 157), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10547 {"evdotpwgssmfraa3", VX (4, 158), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10548 {"evdotpwxgssmfraa3", VX (4, 159), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10549 {"evdotpwcssia", VX (4, 160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10550 {"evdotpwcsmia", VX (4, 161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10551 {"evdotpwcssfra", VX (4, 162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10552 {"evdotpwcssfa", VX (4, 163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10553 {"evdotpwgasmfa", VX (4, 168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10554 {"evdotpwxgasmfa", VX (4, 169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10555 {"evdotpwgasmfra", VX (4, 170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10556 {"evdotpwxgasmfra", VX (4, 171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10557 {"evdotpwgssmfa", VX (4, 172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10558 {"evdotpwxgssmfa", VX (4, 173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10559 {"evdotpwgssmfra", VX (4, 174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10560 {"evdotpwxgssmfra", VX (4, 175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10561 {"evdotpwcssiaaw", VX (4, 176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10562 {"evdotpwcsmiaaw", VX (4, 177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10563 {"evdotpwcssfraaw", VX (4, 178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10564 {"evdotpwcssfaaw", VX (4, 179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10565 {"evdotpwgasmfaa", VX (4, 184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10566 {"evdotpwxgasmfaa", VX (4, 185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10567 {"evdotpwgasmfraa", VX (4, 186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10568 {"evdotpwxgasmfraa", VX (4, 187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10569 {"evdotpwgssmfaa", VX (4, 188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10570 {"evdotpwxgssmfaa", VX (4, 189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10571 {"evdotpwgssmfraa", VX (4, 190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10572 {"evdotpwxgssmfraa", VX (4, 191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10573 {"evdotphihcssi", VX (4, 256), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10574 {"evdotplohcssi", VX (4, 257), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10575 {"evdotphihcssf", VX (4, 258), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10576 {"evdotplohcssf", VX (4, 259), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10577 {"evdotphihcsmi", VX (4, 264), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10578 {"evdotplohcsmi", VX (4, 265), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10579 {"evdotphihcssfr", VX (4, 266), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10580 {"evdotplohcssfr", VX (4, 267), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10581 {"evdotphihcssiaaw3", VX (4, 272), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10582 {"evdotplohcssiaaw3", VX (4, 273), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10583 {"evdotphihcssfaaw3", VX (4, 274), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10584 {"evdotplohcssfaaw3", VX (4, 275), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10585 {"evdotphihcsmiaaw3", VX (4, 280), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10586 {"evdotplohcsmiaaw3", VX (4, 281), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10587 {"evdotphihcssfraaw3", VX (4, 282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10588 {"evdotplohcssfraaw3", VX (4, 283), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10589 {"evdotphihcssia", VX (4, 288), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10590 {"evdotplohcssia", VX (4, 289), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10591 {"evdotphihcssfa", VX (4, 290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10592 {"evdotplohcssfa", VX (4, 291), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10593 {"evdotphihcsmia", VX (4, 296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10594 {"evdotplohcsmia", VX (4, 297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10595 {"evdotphihcssfra", VX (4, 298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10596 {"evdotplohcssfra", VX (4, 299), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10597 {"evdotphihcssiaaw", VX (4, 304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10598 {"evdotplohcssiaaw", VX (4, 305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10599 {"evdotphihcssfaaw", VX (4, 306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10600 {"evdotplohcssfaaw", VX (4, 307), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10601 {"evdotphihcsmiaaw", VX (4, 312), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10602 {"evdotplohcsmiaaw", VX (4, 313), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10603 {"evdotphihcssfraaw", VX (4, 314), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10604 {"evdotplohcssfraaw", VX (4, 315), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10605 {"evdotphausi", VX (4, 320), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10606 {"evdotphassi", VX (4, 321), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10607 {"evdotphasusi", VX (4, 322), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10608 {"evdotphassf", VX (4, 323), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10609 {"evdotphsssf", VX (4, 327), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10610 {"evdotphaumi", VX (4, 328), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10611 {"evdotphasmi", VX (4, 329), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10612 {"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10613 {"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10614 {"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10615 {"evdotphsssi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10616 {"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10617 {"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10618 {"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10619 {"evdotphasusiaaw3", VX (4, 338), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10620 {"evdotphassfaaw3", VX (4, 339), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10621 {"evdotphsssiaaw3", VX (4, 341), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10622 {"evdotphsssfaaw3", VX (4, 343), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10623 {"evdotphaumiaaw3", VX (4, 344), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10624 {"evdotphasmiaaw3", VX (4, 345), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10625 {"evdotphasumiaaw3", VX (4, 346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10626 {"evdotphassfraaw3", VX (4, 347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10627 {"evdotphssmiaaw3", VX (4, 349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10628 {"evdotphsssfraaw3", VX (4, 351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10629 {"evdotphausia", VX (4, 352), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10630 {"evdotphassia", VX (4, 353), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10631 {"evdotphasusia", VX (4, 354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10632 {"evdotphassfa", VX (4, 355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10633 {"evdotphsssfa", VX (4, 359), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10634 {"evdotphaumia", VX (4, 360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10635 {"evdotphasmia", VX (4, 361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10636 {"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10637 {"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10638 {"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10639 {"evdotphsssia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10640 {"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10641 {"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10642 {"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10643 {"evdotphasusiaaw", VX (4, 370), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10644 {"evdotphassfaaw", VX (4, 371), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10645 {"evdotphsssiaaw", VX (4, 373), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10646 {"evdotphsssfaaw", VX (4, 375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10647 {"evdotphaumiaaw", VX (4, 376), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10648 {"evdotphasmiaaw", VX (4, 377), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10649 {"evdotphasumiaaw", VX (4, 378), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10650 {"evdotphassfraaw", VX (4, 379), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10651 {"evdotphssmiaaw", VX (4, 381), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10652 {"evdotphsssfraaw", VX (4, 383), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10653 {"evdotp4hgaumi", VX (4, 384), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10654 {"evdotp4hgasmi", VX (4, 385), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10655 {"evdotp4hgasumi", VX (4, 386), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10656 {"evdotp4hgasmf", VX (4, 387), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10657 {"evdotp4hgssmi", VX (4, 388), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10658 {"evdotp4hgssmf", VX (4, 389), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10659 {"evdotp4hxgasmi", VX (4, 390), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10660 {"evdotp4hxgasmf", VX (4, 391), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10661 {"evdotpbaumi", VX (4, 392), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10662 {"evdotpbasmi", VX (4, 393), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10663 {"evdotpbasumi", VX (4, 394), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10664 {"evdotp4hxgssmi", VX (4, 398), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10665 {"evdotp4hxgssmf", VX (4, 399), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10666 {"evdotp4hgaumiaa3", VX (4, 400), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10667 {"evdotp4hgasmiaa3", VX (4, 401), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10668 {"evdotp4hgasumiaa3", VX (4, 402), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10669 {"evdotp4hgasmfaa3", VX (4, 403), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10670 {"evdotp4hgssmiaa3", VX (4, 404), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10671 {"evdotp4hgssmfaa3", VX (4, 405), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10672 {"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10673 {"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10674 {"evdotpbaumiaaw3", VX (4, 408), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10675 {"evdotpbasmiaaw3", VX (4, 409), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10676 {"evdotpbasumiaaw3", VX (4, 410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10677 {"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10678 {"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10679 {"evdotp4hgaumia", VX (4, 416), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10680 {"evdotp4hgasmia", VX (4, 417), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10681 {"evdotp4hgasumia", VX (4, 418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10682 {"evdotp4hgasmfa", VX (4, 419), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10683 {"evdotp4hgssmia", VX (4, 420), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10684 {"evdotp4hgssmfa", VX (4, 421), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10685 {"evdotp4hxgasmia", VX (4, 422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10686 {"evdotp4hxgasmfa", VX (4, 423), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10687 {"evdotpbaumia", VX (4, 424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10688 {"evdotpbasmia", VX (4, 425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10689 {"evdotpbasumia", VX (4, 426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10690 {"evdotp4hxgssmia", VX (4, 430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10691 {"evdotp4hxgssmfa", VX (4, 431), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10692 {"evdotp4hgaumiaa", VX (4, 432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10693 {"evdotp4hgasmiaa", VX (4, 433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10694 {"evdotp4hgasumiaa", VX (4, 434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10695 {"evdotp4hgasmfaa", VX (4, 435), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10696 {"evdotp4hgssmiaa", VX (4, 436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10697 {"evdotp4hgssmfaa", VX (4, 437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10698 {"evdotp4hxgasmiaa", VX (4, 438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10699 {"evdotp4hxgasmfaa", VX (4, 439), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10700 {"evdotpbaumiaaw", VX (4, 440), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10701 {"evdotpbasmiaaw", VX (4, 441), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10702 {"evdotpbasumiaaw", VX (4, 442), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10703 {"evdotp4hxgssmiaa", VX (4, 446), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10704 {"evdotp4hxgssmfaa", VX (4, 447), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10705 {"evdotpwausi", VX (4, 448), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10706 {"evdotpwassi", VX (4, 449), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10707 {"evdotpwasusi", VX (4, 450), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10708 {"evdotpwaumi", VX (4, 456), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10709 {"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10710 {"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10711 {"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10712 {"evdotpwsssi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10713 {"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10714 {"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10715 {"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10716 {"evdotpwsssiaa3", VX (4, 469), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10717 {"evdotpwaumiaa3", VX (4, 472), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10718 {"evdotpwasmiaa3", VX (4, 473), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10719 {"evdotpwasumiaa3", VX (4, 474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10720 {"evdotpwssmiaa3", VX (4, 477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10721 {"evdotpwausia", VX (4, 480), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10722 {"evdotpwassia", VX (4, 481), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10723 {"evdotpwasusia", VX (4, 482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10724 {"evdotpwaumia", VX (4, 488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10725 {"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10726 {"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10727 {"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10728 {"evdotpwsssia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10729 {"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10730 {"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10731 {"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10732 {"evdotpwsssiaa", VX (4, 501), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10733 {"evdotpwaumiaa", VX (4, 504), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10734 {"evdotpwasmiaa", VX (4, 505), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10735 {"evdotpwasumiaa", VX (4, 506), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10736 {"evdotpwssmiaa", VX (4, 509), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10737 {"evaddib", VX (4, 515), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}},
10738 {"evaddih", VX (4, 513), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}},
10739 {"evsubifh", VX (4, 517), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}},
10740 {"evsubifb", VX (4, 519), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}},
10785 {"circinc", VX (4, 528), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10826 {"evmaxmagws", VX (4, 543), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10827 {"evsl", VX (4, 549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10828 {"evsli", VX (4, 551), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}},
10860 {"evswapbhilo", VX (4, 568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10861 {"evswapblohi", VX (4, 569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10862 {"evswaphhilo", VX (4, 570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10863 {"evswaphlohi", VX (4, 571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10864 {"evswaphe", VX (4, 572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10865 {"evswaphhi", VX (4, 573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10866 {"evswaphlo", VX (4, 574), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10867 {"evswapho", VX (4, 575), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10877 {"evselbitm0", VX (4, 592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10878 {"evselbitm1", VX (4, 593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10879 {"evselbit", VX (4, 594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10880 {"evperm", VX (4, 596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10881 {"evperm2", VX (4, 597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10882 {"evperm3", VX (4, 598), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10884 {"evsrbu", VX (4, 608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10885 {"evsrbs", VX (4, 609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10886 {"evsrbiu", VX (4, 610), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
10887 {"evsrbis", VX (4, 611), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
10888 {"evslb", VX (4, 612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10889 {"evrlb", VX (4, 613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10890 {"evslbi", VX (4, 614), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
10891 {"evrlbi", VX (4, 615), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}},
10892 {"evsrhu", VX (4, 616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10893 {"evsrhs", VX (4, 617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10894 {"evsrhiu", VX (4, 618), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
10895 {"evsrhis", VX (4, 619), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
10896 {"evslh", VX (4, 620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10897 {"evrlh", VX (4, 621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10898 {"evslhi", VX (4, 622), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
10899 {"evrlhi", VX (4, 623), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}},
10900 {"evsru", VX (4, 624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10901 {"evsrs", VX (4, 625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10902 {"evsriu", VX (4, 626), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}},
10903 {"evsris", VX (4, 627), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}},
10904 {"evlvsl", VX (4, 628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10905 {"evlvsr", VX (4, 629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10909 {"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10910 {"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}},
10911 {"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10912 {"evlhhsplath", VX (4, 779), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2, RA}},
10913 {"evlwbsplatwx", VX (4, 786), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10914 {"evlwbsplatw", VX (4, 787), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
10915 {"evlwhsplatwx", VX (4, 794), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10916 {"evlwhsplatw", VX (4, 795), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
10917 {"evlbbsplatbx", VX (4, 798), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10918 {"evlbbsplatb", VX (4, 799), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1, RA}},
10919 {"evstdbx", VX (4, 806), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10920 {"evstdb", VX (4, 807), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8, RA}},
10921 {"evlwbex", VX (4, 810), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10922 {"evlwbe", VX (4, 811), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
10923 {"evlwboux", VX (4, 812), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10924 {"evlwbou", VX (4, 813), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
10925 {"evlwbosx", VX (4, 814), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10926 {"evlwbos", VX (4, 815), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}},
10927 {"evstwbex", VX (4, 818), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10928 {"evstwbe", VX (4, 819), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}},
10929 {"evstwbox", VX (4, 822), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10930 {"evstwbo", VX (4, 823), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}},
10931 {"evstwbx", VX (4, 826), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10932 {"evstwb", VX (4, 827), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}},
10933 {"evsthbx", VX (4, 830), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10934 {"evsthb", VX (4, 831), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2, RA}},
10935 {"evlddmx", VX (4, 832), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10936 {"evlddu", VX (4, 833), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
10937 {"evldwmx", VX (4, 834), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10938 {"evldwu", VX (4, 835), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
10939 {"evldhmx", VX (4, 836), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10940 {"evldhu", VX (4, 837), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
10941 {"evldbmx", VX (4, 838), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10942 {"evldbu", VX (4, 839), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}},
10943 {"evlhhesplatmx", VX (4, 840), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10944 {"evlhhesplatu", VX (4, 841), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
10945 {"evlhhsplathmx", VX (4, 842), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10946 {"evlhhsplathu", VX (4, 843), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
10947 {"evlhhousplatmx", VX (4, 844), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10948 {"evlhhousplatu", VX (4, 845), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
10949 {"evlhhossplatmx", VX (4, 846), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10950 {"evlhhossplatu", VX (4, 847), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}},
10951 {"evlwhemx", VX (4, 848), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10952 {"evlwheu", VX (4, 849), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
10953 {"evlwbsplatwmx", VX (4, 850), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10954 {"evlwbsplatwu", VX (4, 851), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
10955 {"evlwhoumx", VX (4, 852), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10956 {"evlwhouu", VX (4, 853), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
10957 {"evlwhosmx", VX (4, 854), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10958 {"evlwhosu", VX (4, 855), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
10959 {"evlwwsplatmx", VX (4, 856), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10960 {"evlwwsplatu", VX (4, 857), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
10961 {"evlwhsplatwmx", VX (4, 858), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10962 {"evlwhsplatwu", VX (4, 859), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
10963 {"evlwhsplatmx", VX (4, 860), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10964 {"evlwhsplatu", VX (4, 861), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
10965 {"evlbbsplatbmx", VX (4, 862), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10966 {"evlbbsplatbu", VX (4, 863), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1_EX0, RA}},
10967 {"evstddmx", VX (4, 864), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10968 {"evstddu", VX (4, 865), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
10969 {"evstdwmx", VX (4, 866), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10970 {"evstdwu", VX (4, 867), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
10971 {"evstdhmx", VX (4, 868), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10972 {"evstdhu", VX (4, 869), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
10973 {"evstdbmx", VX (4, 870), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10974 {"evstdbu", VX (4, 871), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}},
10975 {"evlwbemx", VX (4, 874), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10976 {"evlwbeu", VX (4, 875), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
10977 {"evlwboumx", VX (4, 876), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10978 {"evlwbouu", VX (4, 877), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
10979 {"evlwbosmx", VX (4, 878), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10980 {"evlwbosu", VX (4, 879), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}},
10981 {"evstwhemx", VX (4, 880), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10982 {"evstwheu", VX (4, 881), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
10983 {"evstwbemx", VX (4, 882), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10984 {"evstwbeu", VX (4, 883), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
10985 {"evstwhomx", VX (4, 884), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10986 {"evstwhou", VX (4, 885), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
10987 {"evstwbomx", VX (4, 886), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10988 {"evstwbou", VX (4, 887), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
10989 {"evstwwemx", VX (4, 888), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10990 {"evstwweu", VX (4, 889), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
10991 {"evstwbmx", VX (4, 890), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10992 {"evstwbu", VX (4, 891), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
10993 {"evstwwomx", VX (4, 892), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10994 {"evstwwou", VX (4, 893), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}},
10995 {"evsthbmx", VX (4, 894), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
10996 {"evsthbu", VX (4, 895), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2_EX0, RA}},
10997 {"evmhusi", VX (4, 1024), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10998 {"evmhssi", VX (4, 1025), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
10999 {"evmhsusi", VX (4, 1026), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11000 {"evmhssf", VX (4, 1028), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11001 {"evmhumi", VX (4, 1029), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11002 {"evmhssfr", VX (4, 1030), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11003 {"evmhesumi", VX (4, 1034), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11004 {"evmhosumi", VX (4, 1038), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11005 {"evmbeumi", VX (4, 1048), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11006 {"evmbesmi", VX (4, 1049), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11007 {"evmbesumi", VX (4, 1050), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11008 {"evmboumi", VX (4, 1052), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11009 {"evmbosmi", VX (4, 1053), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11010 {"evmbosumi", VX (4, 1054), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11011 {"evmhesumia", VX (4, 1066), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11012 {"evmhosumia", VX (4, 1070), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11013 {"evmbeumia", VX (4, 1080), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11014 {"evmbesmia", VX (4, 1081), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11015 {"evmbesumia", VX (4, 1082), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11016 {"evmboumia", VX (4, 1084), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11017 {"evmbosmia", VX (4, 1085), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11018 {"evmbosumia", VX (4, 1086), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11019 {"evmwusiw", VX (4, 1088), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11020 {"evmwssiw", VX (4, 1089), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11021 {"evmwhssfr", VX (4, 1094), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11022 {"evmwehgsmfr", VX (4, 1110), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11023 {"evmwehgsmf", VX (4, 1111), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11024 {"evmwohgsmfr", VX (4, 1118), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11025 {"evmwohgsmf", VX (4, 1119), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11026 {"evmwhssfra", VX (4, 1126), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11027 {"evmwehgsmfra", VX (4, 1142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11028 {"evmwehgsmfa", VX (4, 1143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11029 {"evmwohgsmfra", VX (4, 1150), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11030 {"evmwohgsmfa", VX (4, 1151), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11037 {"evaddh", VX (4, 1160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11038 {"evaddhss", VX (4, 1161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11039 {"evsubfh", VX (4, 1162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11040 {"evsubfhss", VX (4, 1163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11041 {"evaddhx", VX (4, 1164), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11042 {"evaddhxss", VX (4, 1165), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11043 {"evsubfhx", VX (4, 1166), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11044 {"evsubfhxss", VX (4, 1167), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11045 {"evaddd", VX (4, 1168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11046 {"evadddss", VX (4, 1169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11047 {"evsubfd", VX (4, 1170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11048 {"evsubfdss", VX (4, 1171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11049 {"evaddb", VX (4, 1172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11050 {"evaddbss", VX (4, 1173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11051 {"evsubfb", VX (4, 1174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11052 {"evsubfbss", VX (4, 1175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11053 {"evaddsubfh", VX (4, 1176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11054 {"evaddsubfhss", VX (4, 1177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11055 {"evsubfaddh", VX (4, 1178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11056 {"evsubfaddhss", VX (4, 1179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11057 {"evaddsubfhx", VX (4, 1180), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11058 {"evaddsubfhxss", VX (4, 1181), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11059 {"evsubfaddhx", VX (4, 1182), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11060 {"evsubfaddhxss", VX (4, 1183), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11061 {"evadddus", VX (4, 1184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11062 {"evaddbus", VX (4, 1185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11063 {"evsubfdus", VX (4, 1186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11064 {"evsubfbus", VX (4, 1187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11065 {"evaddwus", VX (4, 1188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11066 {"evaddwxus", VX (4, 1189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11067 {"evsubfwus", VX (4, 1190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11068 {"evsubfwxus", VX (4, 1191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11069 {"evadd2subf2h", VX (4, 1192), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11070 {"evadd2subf2hss", VX (4, 1193), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11071 {"evsubf2add2h", VX (4, 1194), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11072 {"evsubf2add2hss", VX (4, 1195), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11073 {"evaddhus", VX (4, 1196), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11074 {"evaddhxus", VX (4, 1197), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11075 {"evsubfhus", VX (4, 1198), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11076 {"evsubfhxus", VX (4, 1199), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11077 {"evaddwss", VX (4, 1201), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11078 {"evsubfwss", VX (4, 1203), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11079 {"evaddwx", VX (4, 1204), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11080 {"evaddwxss", VX (4, 1205), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11081 {"evsubfwx", VX (4, 1206), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11082 {"evsubfwxss", VX (4, 1207), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11083 {"evaddsubfw", VX (4, 1208), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11084 {"evaddsubfwss", VX (4, 1209), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11085 {"evsubfaddw", VX (4, 1210), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11086 {"evsubfaddwss", VX (4, 1211), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11087 {"evaddsubfwx", VX (4, 1212), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11088 {"evaddsubfwxss", VX (4, 1213), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11089 {"evsubfaddwx", VX (4, 1214), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11090 {"evsubfaddwxss", VX (4, 1215), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11116 {"evdivwsf", VX (4, 1228), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11117 {"evdivwuf", VX (4, 1229), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11118 {"evdivs", VX (4, 1230), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11119 {"evdivu", VX (4, 1231), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11120 {"evaddwegsi", VX (4, 1232), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11121 {"evaddwegsf", VX (4, 1233), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11122 {"evsubfwegsi", VX (4, 1234), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11123 {"evsubfwegsf", VX (4, 1235), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11124 {"evaddwogsi", VX (4, 1236), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11125 {"evaddwogsf", VX (4, 1237), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11126 {"evsubfwogsi", VX (4, 1238), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11127 {"evsubfwogsf", VX (4, 1239), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11128 {"evaddhhiuw", VX (4, 1240), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11129 {"evaddhhisw", VX (4, 1241), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11130 {"evsubfhhiuw", VX (4, 1242), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11131 {"evsubfhhisw", VX (4, 1243), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11132 {"evaddhlouw", VX (4, 1244), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11133 {"evaddhlosw", VX (4, 1245), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11134 {"evsubfhlouw", VX (4, 1246), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11135 {"evsubfhlosw", VX (4, 1247), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11136 {"evmhesusiaaw", VX (4, 1282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11137 {"evmhosusiaaw", VX (4, 1286), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11138 {"evmhesumiaaw", VX (4, 1290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11139 {"evmhosumiaaw", VX (4, 1294), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11140 {"evmbeusiaah", VX (4, 1296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11141 {"evmbessiaah", VX (4, 1297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11142 {"evmbesusiaah", VX (4, 1298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11143 {"evmbousiaah", VX (4, 1300), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11144 {"evmbossiaah", VX (4, 1301), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11145 {"evmbosusiaah", VX (4, 1302), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11146 {"evmbeumiaah", VX (4, 1304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11147 {"evmbesmiaah", VX (4, 1305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11148 {"evmbesumiaah", VX (4, 1306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11149 {"evmboumiaah", VX (4, 1308), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11150 {"evmbosmiaah", VX (4, 1309), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11151 {"evmbosumiaah", VX (4, 1310), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11152 {"evmwlusiaaw3", VX (4, 1346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11153 {"evmwlssiaaw3", VX (4, 1347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11154 {"evmwhssfraaw3", VX (4, 1348), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11155 {"evmwhssfaaw3", VX (4, 1349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11156 {"evmwhssfraaw", VX (4, 1350), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11157 {"evmwhssfaaw", VX (4, 1351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11158 {"evmwlumiaaw3", VX (4, 1354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11159 {"evmwlsmiaaw3", VX (4, 1355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11160 {"evmwusiaa", VX (4, 1360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11161 {"evmwssiaa", VX (4, 1361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11162 {"evmwehgsmfraa", VX (4, 1366), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11163 {"evmwehgsmfaa", VX (4, 1367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11164 {"evmwohgsmfraa", VX (4, 1374), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11165 {"evmwohgsmfaa", VX (4, 1375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11166 {"evmhesusianw", VX (4, 1410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11167 {"evmhosusianw", VX (4, 1414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11168 {"evmhesumianw", VX (4, 1418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11169 {"evmhosumianw", VX (4, 1422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11170 {"evmbeusianh", VX (4, 1424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11171 {"evmbessianh", VX (4, 1425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11172 {"evmbesusianh", VX (4, 1426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11173 {"evmbousianh", VX (4, 1428), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11174 {"evmbossianh", VX (4, 1429), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11175 {"evmbosusianh", VX (4, 1430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11176 {"evmbeumianh", VX (4, 1432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11177 {"evmbesmianh", VX (4, 1433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11178 {"evmbesumianh", VX (4, 1434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11179 {"evmboumianh", VX (4, 1436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11180 {"evmbosmianh", VX (4, 1437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11181 {"evmbosumianh", VX (4, 1438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11182 {"evmwlusianw3", VX (4, 1474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11183 {"evmwlssianw3", VX (4, 1475), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11184 {"evmwhssfranw3", VX (4, 1476), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11185 {"evmwhssfanw3", VX (4, 1477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11186 {"evmwhssfranw", VX (4, 1478), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11187 {"evmwhssfanw", VX (4, 1479), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11188 {"evmwlumianw3", VX (4, 1482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11189 {"evmwlsmianw3", VX (4, 1483), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11190 {"evmwusian", VX (4, 1488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11191 {"evmwssian", VX (4, 1489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11192 {"evmwehgsmfran", VX (4, 1494), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11193 {"evmwehgsmfan", VX (4, 1495), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11194 {"evmwohgsmfran", VX (4, 1502), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11195 {"evmwohgsmfan", VX (4, 1503), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11196 {"evseteqb", VX (4, 1536), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11197 {"evseteqb.", VX (4, 1537), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11198 {"evseteqh", VX (4, 1538), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11199 {"evseteqh.", VX (4, 1539), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11200 {"evseteqw", VX (4, 1540), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11201 {"evseteqw.", VX (4, 1541), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11202 {"evsetgthu", VX (4, 1544), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11203 {"evsetgthu.", VX (4, 1545), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11204 {"evsetgths", VX (4, 1546), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11205 {"evsetgths.", VX (4, 1547), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11206 {"evsetgtwu", VX (4, 1548), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11207 {"evsetgtwu.", VX (4, 1549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11208 {"evsetgtws", VX (4, 1550), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11209 {"evsetgtws.", VX (4, 1551), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11210 {"evsetgtbu", VX (4, 1552), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11211 {"evsetgtbu.", VX (4, 1553), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11212 {"evsetgtbs", VX (4, 1554), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11213 {"evsetgtbs.", VX (4, 1555), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11214 {"evsetltbu", VX (4, 1556), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11215 {"evsetltbu.", VX (4, 1557), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11216 {"evsetltbs", VX (4, 1558), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11217 {"evsetltbs.", VX (4, 1559), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11218 {"evsetlthu", VX (4, 1560), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11219 {"evsetlthu.", VX (4, 1561), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11220 {"evsetlths", VX (4, 1562), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11221 {"evsetlths.", VX (4, 1563), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11222 {"evsetltwu", VX (4, 1564), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11223 {"evsetltwu.", VX (4, 1565), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11224 {"evsetltws", VX (4, 1566), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11225 {"evsetltws.", VX (4, 1567), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11226 {"evsaduw", VX (4, 1568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11227 {"evsadsw", VX (4, 1569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11228 {"evsad4ub", VX (4, 1570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11229 {"evsad4sb", VX (4, 1571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11230 {"evsad2uh", VX (4, 1572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11231 {"evsad2sh", VX (4, 1573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11232 {"evsaduwa", VX (4, 1576), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11233 {"evsadswa", VX (4, 1577), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11234 {"evsad4uba", VX (4, 1578), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11235 {"evsad4sba", VX (4, 1579), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11236 {"evsad2uha", VX (4, 1580), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11237 {"evsad2sha", VX (4, 1581), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11238 {"evabsdifuw", VX (4, 1584), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11239 {"evabsdifsw", VX (4, 1585), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11240 {"evabsdifub", VX (4, 1586), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11241 {"evabsdifsb", VX (4, 1587), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11242 {"evabsdifuh", VX (4, 1588), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11243 {"evabsdifsh", VX (4, 1589), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11244 {"evsaduwaa", VX (4, 1592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11245 {"evsadswaa", VX (4, 1593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11246 {"evsad4ubaaw", VX (4, 1594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11247 {"evsad4sbaaw", VX (4, 1595), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11248 {"evsad2uhaaw", VX (4, 1596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11249 {"evsad2shaaw", VX (4, 1597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11250 {"evpkshubs", VX (4, 1600), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11251 {"evpkshsbs", VX (4, 1601), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11252 {"evpkswuhs", VX (4, 1602), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11253 {"evpkswshs", VX (4, 1603), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11254 {"evpkuhubs", VX (4, 1604), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11255 {"evpkuwuhs", VX (4, 1605), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11256 {"evpkswshilvs", VX (4, 1606), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11257 {"evpkswgshefrs", VX (4, 1607), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11258 {"evpkswshfrs", VX (4, 1608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11259 {"evpkswshilvfrs", VX (4, 1609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11260 {"evpksdswfrs", VX (4, 1610), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11261 {"evpksdshefrs", VX (4, 1611), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11262 {"evpkuduws", VX (4, 1612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11263 {"evpksdsws", VX (4, 1613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11264 {"evpkswgswfrs", VX (4, 1614), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11265 {"evilveh", VX (4, 1616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11266 {"evilveoh", VX (4, 1617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11267 {"evilvhih", VX (4, 1618), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11268 {"evilvhiloh", VX (4, 1619), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11269 {"evilvloh", VX (4, 1620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11270 {"evilvlohih", VX (4, 1621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11271 {"evilvoeh", VX (4, 1622), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11272 {"evilvoh", VX (4, 1623), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11273 {"evdlveb", VX (4, 1624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11274 {"evdlveh", VX (4, 1625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11275 {"evdlveob", VX (4, 1626), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11276 {"evdlveoh", VX (4, 1627), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11277 {"evdlvob", VX (4, 1628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11278 {"evdlvoh", VX (4, 1629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11279 {"evdlvoeb", VX (4, 1630), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11280 {"evdlvoeh", VX (4, 1631), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11281 {"evmaxbu", VX (4, 1632), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11282 {"evmaxbs", VX (4, 1633), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11283 {"evmaxhu", VX (4, 1634), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11284 {"evmaxhs", VX (4, 1635), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11285 {"evmaxwu", VX (4, 1636), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11286 {"evmaxws", VX (4, 1637), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11287 {"evmaxdu", VX (4, 1638), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11288 {"evmaxds", VX (4, 1639), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11289 {"evminbu", VX (4, 1640), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11290 {"evminbs", VX (4, 1641), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11291 {"evminhu", VX (4, 1642), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11292 {"evminhs", VX (4, 1643), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11293 {"evminwu", VX (4, 1644), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11294 {"evminws", VX (4, 1645), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11295 {"evmindu", VX (4, 1646), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11296 {"evminds", VX (4, 1647), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11297 {"evavgwu", VX (4, 1648), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11298 {"evavgws", VX (4, 1649), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11299 {"evavgbu", VX (4, 1650), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11300 {"evavgbs", VX (4, 1651), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11301 {"evavghu", VX (4, 1652), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11302 {"evavghs", VX (4, 1653), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11303 {"evavgdu", VX (4, 1654), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11304 {"evavgds", VX (4, 1655), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11305 {"evavgwur", VX (4, 1656), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11306 {"evavgwsr", VX (4, 1657), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11307 {"evavgbur", VX (4, 1658), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11308 {"evavgbsr", VX (4, 1659), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11309 {"evavghur", VX (4, 1660), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11310 {"evavghsr", VX (4, 1661), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11311 {"evavgdur", VX (4, 1662), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
11312 {"evavgdsr", VX (4, 1663), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},