dist/opcodes/d30v-opc.c

208   { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 },
209   { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
210   { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
211   { "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 },
212   { "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
213   { "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
214   { "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
215   { "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
216   { "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
217   { "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
218   { "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
219   { "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
220   { "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
221   { "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
222   { "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
223   { "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, 0, 0, 0 },
224   { "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
225   { "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
236   { "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 },
237   { "cmpu", LOGIC, 0xD, { SHORT_CMPU, LONG_CMP }, EITHER, 0, 0, 0 },
250   { "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
251   { "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
252   { "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
253   { "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
290   { "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 },
291   { "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 },
292   { "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, 0, 0, 0 },
293   { "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
294   { "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 },
298   { "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 },
299   { "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 },
307   { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 },
308   { "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 },
309   { "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 },
310   { "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 },
311   { "src", LOGIC, 0x16, { SHORT_A }, EITHER, FLAG_ADDSUBppp, 0, 0 },
312   { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 },
313   { "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 },
314   { "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 },
315   { "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 },
323   { "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
324   { "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
325   { "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 },
326   { "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
327   { "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
328   { "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
329   { "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
330   { "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
331   { "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
332   { "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
333   { "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
335   { "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
336   { "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, 0, 0, 0 },