Target/X86/X86ISelLowering.cpp

953       setOperationAction(ISD::SMAX, VT, VT == MVT::v8i16 ? Legal : Custom);
1137     setOperationAction(ISD::SMAX,               MVT::v16i8, Legal);
1138     setOperationAction(ISD::SMAX,               MVT::v4i32, Legal);
1352     setOperationAction(ISD::SMAX,      MVT::v4i64,  Custom);
1372       setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1664       setOperationAction(ISD::SMAX,             VT, Legal);
1680       setOperationAction(ISD::SMAX,    VT, HasBWI ? Legal : Custom);
1806       setOperationAction(ISD::SMAX, VT, Legal);
30383   case ISD::SMAX:
40262   // Check for SMAX/SMIN/UMAX/UMIN horizontal reduction patterns.
40265       Extract, BinOp, {ISD::SMAX, ISD::SMIN, ISD::UMAX, ISD::UMIN}, true);
40288   // PHMINPOSUW applies to UMIN(v8i16), for SMIN/SMAX/UMAX we must apply a mask
40292   if (BinOp == ISD::SMAX)
45123     if (MatchMinMax(SMin, ISD::SMAX, C1))
45127   if (SDValue SMax = MatchMinMax(In, ISD::SMAX, C1))
45131         return DAG.getNode(ISD::SMAX, DL, InVT, SMin, In.getOperand(1));
45170     if (SDValue SMax = MatchMinMax(SMin, ISD::SMAX, SignedMin))
45173   if (SDValue SMax = MatchMinMax(In, ISD::SMAX, SignedMin))