Target/AMDGPU/SIFrameLowering.cpp

58   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
68   if (MFI->haveFreeLanesForSGPRSpill(MF, 1)) {
72     if (!MFI->allocateSGPRSpillToVGPR(MF, NewFI))
77     LLVM_DEBUG(auto Spill = MFI->getSGPRToVGPRSpills(NewFI).front();
92     if (TRI->spillSGPRToVGPR() && MFI->allocateSGPRSpillToVGPR(MF, NewFI)) {
98           auto Spill = MFI->getSGPRToVGPRSpills(NewFI).front();
163   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
169   if (MFI->getGITPtrHigh() != 0xffffffff) {
171         .addImm(MFI->getGITPtrHigh())
177   Register GitPtrLo = MFI->getGITPtrLoReg(*MF);
184 // Emit flat scratch setup code, assuming `MFI->hasFlatScratchInit()`
191   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
216     unsigned NumPreloaded = (MFI->getNumPreloadedSGPRs() + 1) / 2;
219     Register GITPtrLoReg = MFI->getGITPtrLoReg(MF);
260         MFI->getPreloadedReg(AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT);
322 static bool allStackObjectsAreDead(const MachineFrameInfo &MFI) {
323   for (int I = MFI.getObjectIndexBegin(), E = MFI.getObjectIndexEnd();
325     if (!MFI.isDeadObjectIndex(I))
340   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
342   assert(MFI->isEntryFunction());
344   Register ScratchRsrcReg = MFI->getScratchRSrcReg();
363   unsigned NumPreloaded = (MFI->getNumPreloadedSGPRs() + 3) / 4;
369   Register GITPtrLoReg = MFI->getGITPtrLoReg(MF);
377       MFI->setScratchRSrcReg(Reg);
404   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
411   assert(MFI->isEntryFunction());
413   Register PreloadedScratchWaveOffsetReg = MFI->getPreloadedReg(
443         MFI->getPreloadedReg(AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER);
465     unsigned NumPreloaded = MFI->getNumPreloadedSGPRs();
468     Register GITPtrLoReg = MFI->getGITPtrLoReg(MF);
484     Register SPReg = MFI->getStackPtrOffsetReg();
491     Register FPReg = MFI->getFrameOffsetReg();
496   if ((MFI->hasFlatScratchInit() || ScratchRsrcReg) &&
502   if (MFI->hasFlatScratchInit()) {
522   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
575     if (MFI->hasImplicitBufferPtr()) {
582           .addReg(MFI->getImplicitBufferPtrUserSGPR())
594           .addReg(MFI->getImplicitBufferPtrUserSGPR())
600         MF.getRegInfo().addLiveIn(MFI->getImplicitBufferPtrUserSGPR());
601         MBB.addLiveIn(MFI->getImplicitBufferPtrUserSGPR());
718   const MachineFrameInfo &MFI = MF.getFrameInfo();
719   return MFI.getStackID(SaveIndex) != TargetStackID::SGPRSpill;
730   const MachineFrameInfo &MFI = MF.getFrameInfo();
747   uint32_t NumBytes = MFI.getStackSize();
795     assert(!MFI.isDeadObjectIndex(FramePtrFI));
813     assert(!MFI.isDeadObjectIndex(BasePtrFI));
832     assert(!MFI.isDeadObjectIndex(FramePtrFI));
834     assert(MFI.getStackID(FramePtrFI) == TargetStackID::SGPRSpill);
849     assert(!MFI.isDeadObjectIndex(BasePtrFI));
851     assert(MFI.getStackID(BasePtrFI) == TargetStackID::SGPRSpill);
903     const unsigned Alignment = MFI.getMaxAlign().value();
976   const MachineFrameInfo &MFI = MF.getFrameInfo();
977   uint32_t NumBytes = MFI.getStackSize();
979                              ? NumBytes + MFI.getMaxAlign().value()
1010     assert(!MFI.isDeadObjectIndex(FramePtrFI));
1024       assert(MFI.getStackID(FramePtrFI) == TargetStackID::SGPRSpill);
1036     assert(!MFI.isDeadObjectIndex(BasePtrFI));
1050       assert(MFI.getStackID(BasePtrFI) == TargetStackID::SGPRSpill);
1098   const MachineFrameInfo &MFI = MF.getFrameInfo();
1100   for (int I = MFI.getObjectIndexBegin(), E = MFI.getObjectIndexEnd();
1102     if (!MFI.isDeadObjectIndex(I) &&
1103         MFI.getStackID(I) == TargetStackID::SGPRSpill &&
1126   MachineFrameInfo &MFI = MF.getFrameInfo();
1132   FuncInfo->removeDeadFrameIndices(MFI);
1139   if (!allStackObjectsAreDead(MFI)) {
1143     RS->addScavengingFrameIndex(FuncInfo->getScavengeFI(MFI, *TRI));
1152   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1153   if (MFI->isEntryFunction())
1183   for (auto SSpill : MFI->getSGPRSpillVGPRs())
1190     assert(!MFI->SGPRForFPSaveRestoreCopy && !MFI->FramePointerSaveIndex &&
1192     getVGPRSpillLaneOrTempRegister(MF, LiveRegs, MFI->SGPRForFPSaveRestoreCopy,
1193                                    MFI->FramePointerSaveIndex, true);
1197     if (MFI->SGPRForFPSaveRestoreCopy)
1198       LiveRegs.addReg(MFI->SGPRForFPSaveRestoreCopy);
1200     assert(!MFI->SGPRForBPSaveRestoreCopy &&
1201            !MFI->BasePointerSaveIndex && "Re-reserving spill slot for BP");
1202     getVGPRSpillLaneOrTempRegister(MF, LiveRegs, MFI->SGPRForBPSaveRestoreCopy,
1203                                    MFI->BasePointerSaveIndex, false);
1211   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1212   if (MFI->isEntryFunction())
1219   SavedRegs.reset(MFI->getStackPtrOffsetReg());
1234     SavedRegs.reset(MFI->getFrameOffsetReg());
1293     const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1294     Register SPReg = MFI->getStackPtrOffsetReg();
1314 static bool frameTriviallyRequiresSP(const MachineFrameInfo &MFI) {
1315   return MFI.hasVarSizedObjects() || MFI.hasStackMap() || MFI.hasPatchPoint();
1322   const MachineFrameInfo &MFI = MF.getFrameInfo();
1326   if (MFI.hasCalls() &&
1333     return MFI.getStackSize() != 0;
1336   return frameTriviallyRequiresSP(MFI) || MFI.isFrameAddressTaken() ||
1353   const MachineFrameInfo &MFI = MF.getFrameInfo();
1358   if (MFI.hasCalls())
1363   return frameTriviallyRequiresSP(MFI);