dev/pci/unichromemode.h

98     {VIASR, SR10, 0xFF, 0x01},
99     {VIASR, SR15, 0x02, 0x02},
100     {VIASR, SR16, 0xBF, 0x08},
101     {VIASR, SR17, 0xFF, 0x1F},
102     {VIASR, SR18, 0xFF, 0x4E},
103     {VIASR, SR1A, 0xFB, 0x08},
104     {VIASR, SR1E, 0x0F, 0x01},
105     {VIASR, SR2A, 0xF0, 0x00},
156   {VIASR,SR10,0xFF,0x01},
157   {VIASR,SR15,0x02,0x02},
158   {VIASR,SR16,0xBF,0x08},
159   {VIASR,SR17,0xFF,0x1F},
160   {VIASR,SR18,0xFF,0x4E},
161   {VIASR,SR1A,0xFB,0x82},
162   {VIASR,SR1B,0xFF,0xF0},
163   {VIASR,SR1F,0xFF,0x00},
164   {VIASR,SR1E,0xFF,0xF1},
165   {VIASR,SR22,0xFF,0x1F},
166   {VIASR,SR2A,0x0F,0x0F},
167   {VIASR,SR2E,0xFF,0xFF},
168   {VIASR,SR3F,0xFF,0xFF},
169   {VIASR,SR40,0xFF,0x00},
170   {VIASR,CR30,0xFF,0x04},
225     {VIASR, SR10, 0xFF, 0x01},          /* Unlock Register                     */
226     {VIASR, SR16, 0xFF, 0x08},          /* Display FIFO threshold Control      */
227     {VIASR, SR17, 0xFF, 0x1F},          /* Display FIFO Control                */
228     {VIASR, SR18, 0xFF, 0x4E},          /* GFX PREQ threshold                  */
229     {VIASR, SR1A, 0xFF, 0x0a},          /* GFX PREQ threshold                  */
230     {VIASR, SR1F, 0xFF, 0x00},          /* Memory Control 0                    */
231     {VIASR, SR1B, 0xFF, 0xF0},          /* Power Management Control 0          */
232     {VIASR, SR1E, 0x0F, 0x01},          /* Power Management Control            */
233     {VIASR, SR20, 0xFF, 0x00},          /* Sequencer Arbiter Control 0         */
234     {VIASR, SR21, 0xFF, 0x00},          /* Sequencer Arbiter Control 1         */
235     {VIASR, SR22, 0xFF, 0x1F},          /* Display Arbiter Control 1           */
236     {VIASR, SR2A, 0xF0, 0x00},          /* Power Management Control 5          */
237     {VIASR, SR2D, 0xFF, 0xFF},          /* Power Management Control 1          */
238     {VIASR, SR2E, 0xFF, 0xFF},          /* Power Management Control 2          */
285     {VIASR, SR10, 0xFF, 0x01},
286     {VIASR, SR15, 0x02, 0x02},
287     {VIASR, SR16, 0xBF, 0x08},
288     {VIASR, SR17, 0xFF, 0x1F},
289     {VIASR, SR18, 0xFF, 0x4E},
290     {VIASR, SR1A, 0xFB, 0x08},
291     {VIASR, SR1B, 0xFF, 0xF0},
292     {VIASR, SR1E, 0x0F, 0x01},
293     {VIASR, SR2A, 0xF0, 0x00},
349   {VIASR,SR1E,0xF0,0xF0},
350   {VIASR,SR2A,0x0F,0x0F},
351   {VIASR,SR15,0x02,0x02},
352   {VIASR,SR16,0xBF,0x08},
353   {VIASR,SR17,0xFF,0x1F},
354   {VIASR,SR18,0xFF,0x4E},
355   {VIASR,SR1A,0xFB,0x08},
393   {VIASR,0x16,0xBF,0x0C},
394   {VIASR,0x18,0xFF,0x4C}